PM7311 pmc-sierra, PM7311 Datasheet - Page 270

• Manufacturer Part Number: PM7311
• Description: Freedm 84a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021832, Issue 2
Figure 47 Transmit APPI Timing (Special Conditions)
Figure 47 shows two special conditions – (1) the transfer of a one word packet, illustrating how
the external controller must wait until TRDY has been sampled high before the next data transfer
can begin, and (2) the transfer of a packet that completes when TRDY is set low, illustrating that
although the packet has been completely transferred, the external controller must still wait until
TRDY has been sampled high before the next data transfer can begin.
The first data transfer is a single word packet for Any-PHY channel 0. The FREEDM 84A1024L
asserts TRDY high one TXCLK cycle after TSX is sampled high. The Tx APPI protocol dictates
that the external controller must wait until one clock after TRDY is sampled high before
beginning the next data transfer for Any-PHY channel 3. The external controller must hold the
last valid word on TXDATA[15:0] until TRDY is sampled high. In this case, that data is a don’t
care. The FREEDM 84A1024L tristates the TRDY signal one TXCLK cycle after it has been
driven high.
The second transfer is a three word packet, which completes transfer in the same TXCLK cycle
that TRDY is sampled low by the external controller. Again, the external controller must hold the
last valid word on TXDATA[15:0] until TRDY is sampled high. In this case, that data is D2, the
last word of the packet. The FREEDM 84A1024L may drive TRDY low for an indeterminate
number of TXCLK cycles. During this time, the external controller must wait and is not
permitted to begin another burst data transfer until TRDY is sampled high. When the external
controller samples TRDY high, the current burst transfer is deemed to be complete and the
external controller may begin the next data transfer. The FREEDM 84A1024L tristates the
TRDY signal one TXCLK cycle after it has been driven high.
Figure 48 Transmit APPI Poll Timing
When supporting Any-PHY Level 2, polling is completely decoupled from device and Any-PHY
channel selection on the Tx APPI (Figure 48). Accordingly, the TXADDR[15:0] signals continue
to provide only a poll address for any of the FREEDM 84A1024L devices sharing the Tx APPI.
The FREEDM 84A1024L compares the TXADDR[15:0] to the base and range address registers
to determine if the channel being polled resides within the device. Poll results are returned on the
TPA signals. The meaning of the TPA responses depends on the setting of the TPA_MODE bit in
TPA_LO, TPA_HI
TXADDR[15:0]
TXCLK
TXDATA[15:0]
TXCLK
TRDY
TMOD
TEOP
TERR
TSX
CH 1023
CH 0
CH 0
D0
CH 1023
CH 254
FREEDM 84A1024L ASSP Telecom Standard Product Data Sheet
CH 8
CH 0
CH 3
CH 254
D0
NULL
D1
CH 8
D2
CH 0
CH 2
CH 399
D0
CH 0
NULL
Released
NULL1
CH 399
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