PM7311 pmc-sierra, PM7311 Datasheet - Page 216

• Manufacturer Part Number: PM7311
• Description: Freedm 84a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021832, Issue 2
Register 0x9A0: BIST Controller
This control register is common to all BIST sequencers in the FREEDM 84A1024L.
The BIST Enable register must be set up prior to setup of this register.
BISTSIDE
BISTMODE[2:0]
BIST_PATTERN[7:0]
The BIST sequencer input BISTSIDE determines which port of dual-port RAMs is tested
when the BIST logic is operating.
The BIST sequencer input BISTMODE should be set to “010” to run BIST. Other values are
reserved for use during PMC production test.
The BIST test data pattern that is applied to the RAMs during BIST.
Bit
Bit 31
To
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FREEDM 84A1024L ASSP Telecom Standard Product Data Sheet
Function
Unused
BISTPATTERN[7]
BISTPATTERN[6]
BISTPATTERN[5]
BISTPATTERN[4]
BISTPATTERN[3]
BISTPATTERN[2]
BISTPATTERN[1]
BISTPATTERN[0]
BISTMODE[2]
BISTMODE[1]
BISTMODE[0]
BISTSIDE
Default
X
0
0
0
0
0
0
0
0
1
0
0
0
Released
216