PM7311 pmc-sierra, PM7311 Datasheet - Page 273

• Manufacturer Part Number: PM7311
• Description: Freedm 84a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021832, Issue 2
Figure 51 Transmit APPI Timing Any-PHY Level 3 (Special Condition)
Figure 51 shows a special condition where the transfer of a packet that completes when TRDY is
set low, illustrating that although the packet has been completely transferred, the external
controller must still wait until TRDY has been sampled high before the next data transfer can
begin.
The illustrated transfer is a two byte packet, which completes transfer in the same TXCLK cycle
that TRDY is sampled low by the external controller. The external controller must hold the last
valid byte on TXDATA[7:0] until TRDY is valid and sampled high. In this case, that data is D1,
the last byte of the packet. The FREEDM 84A1024L may drive TRDY low for an indeterminate
number of TXCLK cycles. During this time, the external controller must wait and is not
permitted to begin another burst data transfer until TRDY is valid and sampled high. When the
external controller samples TRDY high, the current burst transfer is deemed to be complete and
the external controller may begin the next data transfer.
Figure 52 Transmit APPI Polling Timing (Any-PHY Level 3)
TPA_LO, TPA_HI
When supporting Any-PHY Level 3 mode polling is completely decoupled from data transfer on
the Tx APPI (Figure 52) with the restriction that the TPA poll result is invalid for all channels if it
corresponds to a TXADDR poll coincident with the start of transfer (i.e. the cycle in which TSX
is driven high). Accordingly, the TXADDR[15:0] signals continue to provide only a poll address
for the FREEDM 84A1024L device The FREEDM 84A1024L compares the TXADDR[15:0] to
the base and range address registers to determine if the Any-PHY channel being polled resides
within the device. Poll results are returned on the TPA signal. The meaning of the TPA responses
depends on the setting of the TPA_MODE bit in the TFRAG Any-PHY Channel RAM. The user
may configure TPA_HI/TPA_LO to report whether or not space exists in the Any-PHY channel
FIFO to accept a further MTU-sized packet. Alternatively, TPA_HI/ TPA_LO may be configured
to report whether the FIFO fill level is above or below a user-defined threshold.
TXADDR[15:0]
TXDATA[7:0]
TXCLK
TXCLK
TRDY
TERR
TEOP
TSX
CH 1023
CH 0
CH 1023
CH 254
FREEDM 84A1024L ASSP Telecom Standard Product Data Sheet
CH 8
CH 0
CH 3
CH3
CH 254
D0
NULL
CH 8
D1
CH 0
CH2
CH 399
CH2
CH 0
D0
NULL
D1
Released
NULL1
CH 399
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