PM7311 pmc-sierra, PM7311 Datasheet - Page 31

• Manufacturer Part Number: PM7311
• Description: Freedm 84a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021832, Issue 2
Pin Name
DDP
DPL
DV5
ADATA[0]
ADATA[1]
ADATA[2]
ADATA[3]
ADATA[4]
ADATA[5]
ADATA[6]
ADATA[7]
ADP
Type
Input
Input
Input
Tristate
Output
Tristate
Output
Pin
No.
V31
V30
V29
L28
L29
L30
M27
M28
M29
M30
M31
N27
FREEDM 84A1024L ASSP Telecom Standard Product Data Sheet
Function
The SBI DROP bus parity signal (DDP) carries the even or
odd parity for the DROP bus signals. The parity calculation
encompasses the DDATA[7:0], DPL and DV5 signals.
Multiple PHY devices can drive DDP at uniquely assigned
tributary column positions. This parity signal is intended to
detect accidental PHY source clashes in the column
assignment.
DDP is sampled on the rising edge of REFCLK.
The SBI DROP bus payload signal (DPL) indicates valid data
within the SBI TDM bus structure. This signal is asserted
during all octets making up a tributary. This signal may be
asserted during the V3 or H3 octet within a tributary to
accommodate negative timing adjustments between the
tributary rate and the fixed TDM bus structure. This signal
may be de-asserted during the octet following the V3 or H3
octet within a tributary to accommodate positive timing
adjustments between the tributary rate and the fixed TDM bus
structure.
Multiple PHY devices can drive DPL at uniquely assigned
tributary column positions.
DPL is sampled on the rising edge of REFCLK.
The SBI DROP bus payload indicator signal (DV5) locates
the position of the floating payloads for each tributary within
the SBI TDM bus structure. Timing differences between the
port timing and the TDM bus timing are indicated by
adjustments of this payload indicator relative to the fixed TDM
bus structure.
Multiple PHY devices can drive DV5 at uniquely assigned
tributary column positions. All movements indicated by this
signal must be accompanied by appropriate adjustments in
the DPL signal.
DV5 is sampled on the rising edge of REFCLK.
The SBI ADD bus data signals (ADATA[7:0]) contain the time
division multiplexed transmit data from the up to 84
independently timed links. Data from each link is transported
as a tributary within the SBI TDM bus structure. Multiple link
layer devices can drive the SBI ADD bus at uniquely
assigned tributary column positions. When the FREEDM
84A1024L is not outputting data on a particular tributary
column the ADATA[7:0] are driven or tri-stated based on the
DEFAULT_DRV register value.
ADATA[7:0] are updated on the rising edge of REFCLK.
The SBI ADD bus parity signal (ADP) carries the even or odd
parity for the ADD bus signals. The parity calculation
encompasses the ADATA[7:0], APL and AV5 signals.
Multiple link layer devices can drive this signal at uniquely
assigned tributary column positions. When the FREEDM
84A1024L is not outputting data on a particular tributary
column, ADP is driven or tri-stated based on the
DEFAULT_DRV register value. This parity signal is intended
to detect accidental link layer source clashes in the column
assignment.
ADP is updated on the rising edge of REFCLK.
Released
31