PM7311 pmc-sierra, PM7311 Datasheet - Page 124

• Manufacturer Part Number: PM7311
• Description: Freedm 84a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021832, Issue 2
CHANGEI
ERRORI
DLLREFCLKI
DLLSYSCLKI
The delay line tap change event register bit (CHANGEI) indicates the CHANGE register bit
has changed value. When the CHANGE register changes from a logic zero to a logic one, the
CHANGEI register bit is set to logic one.
The delay line error event register bit (ERRORI) indicates the ERROR register bit has gone
high. When the ERROR register changes from a logic zero to a logic one, the ERRORI
register bit is set to logic one. If the ERRORE interrupt enable is high, the DLLI bit in the
Master High Priority Interrupt Status Register is also asserted when ERRORI asserts.
The reference clock event register bit DLLREFCLKI provides a method to monitor activity
on the reference clock to the DLL. This reference clock is the feedback path from the far end
of the clock tree to which the system clock is synchronized. When the DLLREFCLK primary
input changes from a logic zero to a logic one, the DLLREFCLKI register bit is set to logic
one.
The system clock event register bit DLLSYSLCKI provides a method to monitor activity on
the system clock (SYSCLK). When the SYSCLK primary input changes from a logic zero to
a logic one, the DLLSYSCLKI register bit is set to logic one. The DLLSYSCLKI register bit
is cleared immediately after it is read, thus acknowledging the event has been recorded.
FREEDM 84A1024L ASSP Telecom Standard Product Data Sheet
Released
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