PM7311 pmc-sierra, PM7311 Datasheet - Page 105

• Manufacturer Part Number: PM7311
• Description: Freedm 84a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021832, Issue 2
UECCCBI
UECCRSI
SRAMPI
TFUDRI
TFOVRI
TPRTYI
The Uncorrected ECC Error detected on Chunk Buffer Memory interrupt status bit reports
such an event to the microprocessor. UECCCBI is set high when an ECC Error that could not
be corrected is detected during a memory access to the Chunk Buffer Memory. When set, the
CB_DRAMC_UNCOECCE Register will hold the last DRAM address that was being
accessed when an ECC Error occurred. UECCCBI and CB_DRAMC_UNCOECCE remain
valid when interrupts are disabled and may be polled to detect error events.
The Uncorrected ECC Error detected on Re-sequencing Memory interrupt status bit reports
such an event to the microprocessor. UECCRSI is set high when an ECC Error that could not
be corrected is detected during a memory access to the Re-sequencing Memory. When set, the
RS_DRAMC_UNCOECCE Register will hold the last DRAM address that was being
accessed when an ECC Error occurred. UECCRSI and RS_DRAMC_UNCOECCE remain
valid when interrupts are disabled and may be polled to detect error events.
SRAM Parity Error interrupt status bit reports parity error interrupts to the microprocessor.
SRAMPI is set high whenever a parity error is detected on accesses to external SRAM. When
set, the SRAM Parity Error Address (SPERRADD) Register will hold the last SRAM address
that was being accessed when a parity error occurred. SRAMPI and SPERRADD remain
valid when interrupts are disabled and may be polled to detect error events.
The transmit Partial Packet FIFO underflow error interrupt status bit reports transmit Partial
Packet FIFO underflow error interrupts to the microprocessor. TFUDRI is set high upon
attempts to read data from the logical FIFO when it is already empty. TFUDRI remains valid
when interrupts are disabled and may be polled to detect transmit FIFO underflow events.
The transmit Partial Packet FIFO overflow error interrupt status bit reports transmit Partial
Packet FIFO overflow error interrupts to the microprocessor. TFOVRI is set high upon
attempts to write data to the logical FIFO when it is already full. TFOVRI remains valid
when interrupts are disabled and may be polled to detect transmit FIFO overflow events.
The transmit parity error interrupt status bit reports the detection of a parity error on the
transmit APPI. TPRTYI is set high upon detection of a parity error. TPRTYI remains valid
when interrupts are disabled and may be polled to detect parity errors.
FREEDM 84A1024L ASSP Telecom Standard Product Data Sheet
Released
105