PM7311 pmc-sierra, PM7311 Datasheet - Page 82

• Manufacturer Part Number: PM7311
• Description: Freedm 84a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021832, Issue 2
10.9.9
The writer controller provides a means for writing data from the Tx APPI into the FIFO. The
whisper controller provides the Any-PHY channel address of the data being written into the FIFO.
As soon as the first word of data has been written into the FIFO, the whisper controller provides
the Any-PHY channel information for that data to the downstream block. The whisper controller
will wait for acknowledgement and the reader controller is then requested to read the data from
the FIFO. Once the reader controller has commenced the data transfer, the whisper controller will
provide the Any-PHY channel information for next data transfer received, if any.
The reader controller provides a means of reading data out of the FIFO. When the writer
controller indicates that data has been written into the FIFO, the reader controller is permitted to
read that data. The reader controller will then wait for a request for data from the downstream
block. Because the reader controller reads data out of the FIFO in the order in which they were
filled, the TFRAG block will request data for Any-PHY channels in the order in which they were
whispered.
Polling Control and Management
The TAPI-12 only responds to poll addresses that are identified by the base and range address
registers in the TAPI-12 Control registers. The TAPI-12 maintains a mirror image of the status of
each channel FIFO in the EQM-12. The EQM-12 continuously reports the status of the 2048
FIFOs (1024 channels x 2 priority levels) to the TAPI-12 and the TAPI-12 updates the mirror
image accordingly.
Transmit Fragmentor (TFRAG)
Datagrams are transferred from the upstream device to the FREEDM 84A1024L via the Any-
PHY interface. The transmit fragmentor fragments (if required) the packet, encapsulates the
fragments with a sequence number (in multi-link or fragmentation situations), assigns the
datagram to an HDLC channel and segments the datagram into chunks for storage in the external
SDRAM.
When supporting a multi-link bundle, the address prepend and the connection identifier that is
provided on the Any-PHY interface are used to index the appropriate sequence number and an
index to the HDLC channels associated with the multi-link bundle. The sequence number and
additional header bits (B, E, and COS) are appended to arriving datagrams. The datagram is
assigned to an HDLC channel in the multi-link bundle. HDLC channel assignment is based on the
current occupancy of the HDLC channels in a multi-link bundle. The datagram is assigned to the
HDLC channel with the lowest number of bytes in the channel queue.
Compressed PPP headers are detected by the TFRAG. The TFRAG is capable of appending
sequence numbers onto multi-link packets with compressed headers.
On a per HDLC channel and per priority basis these datagrams are segmented into chunks and are
stored in an external SDRAM memory. A HDLC chunk will only consist of data from one
packet/frame. Segmented data is encapsulated (Figure 26) to form a 36 byte storage element. The
encapsulation contains the next address pointer, the size and a local integrity check that covers the
address field. The next address pointer is used to create a linked list of chunks that comprise a
datagram.
The address indicates where the next chunk of the datagram is located in the external memory.
This effectively links the chunks of a datagram in external memory. In the last data chunk, the
FREEDM 84A1024L ASSP Telecom Standard Product Data Sheet
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