PM7311 pmc-sierra, PM7311 Datasheet - Page 32

• Manufacturer Part Number: PM7311
• Description: Freedm 84a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021832, Issue 2
Pin Name
APL
AV5
ADETECT[0]
ADETECT[1]
AJUST_REQ
AACTIVE
Type
Tristate
Output
Tristate
output
Input
Input
Output
Pin
No.
N28
N30
P28
P29
N31
P27
FREEDM 84A1024L ASSP Telecom Standard Product Data Sheet
Function
The SBI ADD bus payload signal (APL) indicates valid data
within the SBI TDM bus structure. This signal is asserted
during all octets making up a tributary. This signal may be
asserted during the V3 or H3 octet within a tributary to
accommodate negative timing adjustments between the
tributary rate and the fixed TDM bus structure. This signal
may be de-asserted during the octet following the V3 or H3
octet within a tributary to accommodate positive timing
adjustments between the tributary rate and the fixed TDM bus
structure.
Multiple link layer devices can drive this signal at uniquely
assigned tributary column positions. When the FREEDM
84A1024L is not outputting data on a particular tributary
column, APL is driven or tri-stated based on the
DEFAULT_DRV register value.
APL is updated on the rising edge of REFCLK.
The SBI ADD bus payload indicator signal (AV5) locates the
position of the floating payloads for each tributary within the
SBI TDM bus structure. Timing differences between the port
timing and the TDM bus timing are indicated by adjustments
of this payload indicator relative to the fixed TDM bus
structure.
Multiple link layer devices can drive this signal at uniquely
assigned tributary column positions. When the FREEDM
84A1024L is not outputting data on a particular tributary
column, AV5 is driven or tri-stated based on the
DEFAULT_DRV register value.
AV5 is updated on the rising edge of REFCLK.
The SBI ADD bus conflict detection signals (ADETECT[1:0])
may be connected to the AACTIVE outputs of other link layer
devices sharing the SBI ADD bus. FREEDM 84A1024L will
tristate the SBI ADD bus signals ADATA[7:0], ADP, APL and
AV5 if either of ADETECT[1] and ADETECT[0] is asserted.
ADETECT[1:0] are asynchronous inputs.
The SBI ADD bus justification request signal (AJUST_REQ)
is used to speed up or slow down the output data rate of the
FREEDM 84A1024L.
Negative timing adjustments are requested by asserting
AJUST_REQ during the V3 or H3 octet of the drop bus
depending on the tributary type. In response to this the
FREEDM 84A1024L will send an extra byte in the V3 or H3
octet of the next frame on the add bus along with a valid APL
indicating a negative justification.
Positive timing adjustments are requested by asserting
AJUST_REQ during the octet following the V3 or H3 octet of
the drop bus, depending on the tributary type. FREEDM
84A1024L will respond to this by not sending an octet during
the octet following the V3 or H3 octet of the next frame on the
add bus and de-asserting APL to indicate a positive
justification.
AJUST_REQ is sampled on the rising edge of REFCLK.
The SBI ADD bus active indicator signal (AACTIVE) is
asserted whenever FREEDM 84A1024L is driving the SBI
Released
32