PM7311 pmc-sierra, PM7311 Datasheet - Page 71

• Manufacturer Part Number: PM7311
• Description: Freedm 84a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021832, Issue 2
Figure 16 HDLC Frame
The CRC algorithm for the frame checking sequence (FCS) field is either a CRC-CCITT or CRC-
32 function. Figure 17 shows a CRC encoder block diagram using the generating polynomial g
(X) = 1 + g
generating polynomial g (X) = 1 + X
has a generating polynomial g (X) = 1 + X + X
+ X
Figure 17 CRC Generator
The partial packet buffer processor controls the 64 Kbyte partial packet RAM, which is divided
into 4K 16 byte blocks. A block pointer RAM is used to chain the partial packet blocks into
circular HDLC channel FIFO buffers. Thus, non-contiguous sections of the RAM can be
allocated in the partial packet buffer RAM to create an HDLC channel FIFO. System software is
responsible for the assignment of blocks to individual HDLC channel FIFOs. Figure 18 shows an
example of three blocks (blocks 1, 3, and 200) linked together to form a 48 byte HDLC channel
FIFO.
Partial Packet Buffer Processor
22
+ X
23
1
X + g
+ X
Flag
26
2
D
X
0
+ X
2
LSB
+…+ g
32
. The first FCS bit received is the residue of the highest term.
g
1
n-1
Information
X
D
1
n-1
FREEDM 84A1024L ASSP Telecom Standard Product Data Sheet
5
HDLC Packet
+ X
+ X
g
Parity Check Digits
2
n
12
. The CRC-CCITT FCS is two bytes in size and has a
+ X
2
D
2
+ X
16
. The CRC-32 FCS is four bytes in size and
4
FCS
+ X
5
g
n-1
+ X
7
Flag
D
+ X
n-1
MSB
8
+ X
10
Flag
Message
+ X
11
+ X
Released
12
+ X
71
16