PM7311 pmc-sierra, PM7311 Datasheet - Page 144

• Manufacturer Part Number: PM7311
• Description: Freedm 84a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021832, Issue 2
Register 0x384: THDL Indirect Channel Data #1
This register contains data read from the channel provision RAM after an indirect channel read
operation or data to be inserted into the channel provision RAM in an indirect channel write
operation.
FPTR[11:0]
DELIN
The indirect FIFO block pointer (FPTR[11:0]) informs the partial packet buffer processor
about the circular linked list of blocks to use for a FIFO for the channel. The FIFO pointer to
be written to the channel provision RAM, in an indirect write operation, must be set up in this
register before triggering the write. The FIFO pointer value can be any one of the block
numbers provisioned, by indirect block write operations, to form the circular buffer.
The indirect delineate enable bit (DELIN) configures the HDLC processor to perform flag
sequence insertion and bit stuffing on the outgoing data stream. The delineate enable bit to
be written to the channel provision RAM, in an indirect channel write operation, must be set
up in this register before triggering the write. When DELIN is set high, flag sequence
insertion, bit stuffing and ,optionally, CRC generation is performed on the outgoing HDLC
data stream. When DELIN is set low, the HDLC processor does not perform any processing
(flag sequence insertion, bit stuffing nor CRC generation) on the outgoing stream. DELIN
reflects the value written until the completion of a subsequent indirect channel read operation.
Bit
Bit 31
To
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FREEDM 84A1024L ASSP Telecom Standard Product Data Sheet
Function
Unused
PROV
CRC[1]
CRC[0]
DELIN
FPTR[11]
FPTR[10]
FPTR[9]
FPTR[8]
FPTR[7]
FPTR[6]
FPTR[5]
FPTR[4]
FPTR[3]
FPTR[2]
FPTR[1]
FPTR[0]
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Released
144