PM7311 pmc-sierra, PM7311 Datasheet - Page 268

• Manufacturer Part Number: PM7311
• Description: Freedm 84a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021832, Issue 2
14.6 Transmit APPI Timing (Any-PHY Level 2)
84A1024L completes the burst data transfer and tristates the Rx APPI one RXCLK cycle after
RENB is sampled high. Because the burst data transfer is complete and RENB is immediately
returned low following selection, the FREEDM 84A1024L immediately begins the next data
transfer following the single turn-around cycle.
The protocol dictates that at least one tristate turn-around cycle be inserted between data
transfers, even if the external controller is reselecting the same FREEDM 84A1024L device. In
other words, Figure 44 shows the earliest possible time that the external controller could have set
RENB high to reselect FREEDM 84A1024L device 0.
Figure 45 Receive APPI Timing (Boundary Condition)
RXDATA[15:0]
Figure 45 shows the boundary condition where a packet transfer completes shortly after the
external controller has set RENB high to pause the FREEDM 84A1024L device. The second data
transfer is the final two words of a packet for FREEDM 84A1024L device 7, channel 1.
When FREEDM 84A1024L device 0 places D2 on RXDATA[15:0], the external controller sets
RENB high to pause the FREEDM 84A1024L device. In the following RXCLK cycle, the
FREEDM 84A1024L provides D3 on RXDATA[15:0] and sets REOP high to conclude packet
transfer. The external controller samples REOP high while RENB is high and recognizes that the
packet transfer is complete. The external controller now knows that it doesn’t need to reselect
FREEDM 84A1024L device 0, but can select another FREEDM 84A1024L device sharing the Rx
APPI. The external controller decides to select FREEDM 84A1024L device 7 by placing this
address on the RXADDR[3:0] signals. The external controller sets RENB low to commence data
transfer from FREEDM 84A1024L device 7.
The transmit Any-PHY packet interface (APPI) timing is shown in Figure 46. An external
controller provides data to the FREEDM 84A1024L device using the transmit APPI. The
following discussion surrounding the transmit APPI functional timing assumes that multiple
FREEDM 84A1024L devices share a single external controller. The FREEDM 84A1024L
compares the TXADDR[15:0] to the base and range address registers to determine if the poll
request is destined for the particular FREEDM 84A1024L. All Tx APPI signals are shared
between the FREEDM 84A1024L devices.
RXADDR[3:0]
RXCLK
RMOD
REOP
RENB
RERR
RVAL
RSOP
RPA
RSX
Dev 0
NULL
Dev 7
Dev 0
NULL
CH 2
Dev 6
Dev 7
D0
FREEDM 84A1024L ASSP Telecom Standard Product Data Sheet
NULL
D1
Dev 6
Dev 4
D2
D3
NULL
Dev 4
Dev 7
Dev 1
Dev 7
NULL
Dev 3
Dev 1
CH 1
Dev 7
Dev 7
NULL
D8
Released
Dev 2
Dev 3
D9
268
NULL
Dev 2