PM7311 pmc-sierra, PM7311 Datasheet - Page 66

• Manufacturer Part Number: PM7311
• Description: Freedm 84a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021832, Issue 2
10.4 Loop Back
10.4.1
10.4.2
10.4.3
10.5 Initialization Process
10.5.1
Data arriving at the SBI interface is inserted into the SBI format at the correct tributary and
timeslot associated with a HDLC channel. In addition to the SBI bus, 3 clock and data interfaces
are also supported.
Clock and Data Loop Back
The line loop back enable bits in the Master Line Loop back Register control line loop back for
the three serial clock and data links. When loop back is enabled, the data on RD[n] is passed
verbatim to TD[n], which is then updated on the falling edge of RCLK[n]. TCLK[n] is ignored.
When loop back is disabled, TD[n] is processed normally.
SBI Line Loop Back
When enabled, the data on tributary #n output by the EXSBI block is looped back to the tributary
#n in the INSBI block. (Note: The FREEDM must be the master of the tributary to enable SBI
line loop back.)
When loop back is disabled, transmit data for tributary #n is provided by the TCAS-12 block (i.e.
processed normally).
System Side Loop Back
The loop back controller block in the RCAS-12 TSB implements the channel based diagnostic
loop back function. Every valid data byte belonging to a channel with diagnostic loop back
enabled from the Transmit HDLC Processor / Partial Packet Buffer block (THDL-12) is written
into a 1024 word FIFO in the RCAS-12 block. The loop back controller monitors for an idle
time-slot or a time-slot carrying a channel with diagnostic loop back enabled. If either condition
holds, the current data byte is replaced by data retrieved from the loop back data FIFO.
Configuration of a channel/CI cannot be changed while data is flowing on that channel/CI.
CB and RS Memory FPP Initialization
1. After a hardware or software reset is issued, the chip goes into an initialization sequence. The
2. Wait for SDRAM_INIT to be cleared in XX_DRAMC Status and Control Registers
3. Test memories if desired by s/w.
4. FPP FIFO Initialization
RST_DONEI bit in the F84 Master High Priority Interrupt Status register will indicate when
this sequence is complete. At this stage, all the registers and memories internal to the chip and
the external SRAM can be accessed.
(PROV_MODE will also be set at this point).
o Option 1 (s/w init)
·
Write ECC_OFF bit as desired
FREEDM 84A1024L ASSP Telecom Standard Product Data Sheet
Released
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