PM7311 pmc-sierra, PM7311 Datasheet - Page 6

• Manufacturer Part Number: PM7311
• Description: Freedm 84a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021832, Issue 2
11 Normal Mode Register Description .....................................................................................100
12 Test Features Description....................................................................................................257
13 Operation .............................................................................................................................259
14 Functional Timing ................................................................................................................263
15 Absolute Maximum Ratings.................................................................................................278
16 Normal Operating Conditions ..............................................................................................279
17 Power Information ...............................................................................................................280
18 D.C. Characteristics.............................................................................................................282
19 A.C. Timing Characteristics .................................................................................................283
10.3 Packet Walkthrough.....................................................................................................63
10.4 Loop Back ....................................................................................................................66
10.5 Initialization Process ....................................................................................................66
10.6 Any-PHY Tear Down Procedure ..................................................................................67
10.7 CI Tear Down Procedure .............................................................................................67
10.8 Restrictions on Any-PHY to CI Mapping ......................................................................68
10.9 Block Descriptions .......................................................................................................69
11.1 Microprocessor Accessible Registers ........................................................................100
11.2 Microprocessor Accessible Memories .......................................................................236
12.1 Test Mode Registers ..................................................................................................257
12.2 JTAG Test Port...........................................................................................................257
13.1 JTAG Support ............................................................................................................259
14.1 SBI Drop Bus Interface Timing ..................................................................................263
14.2 SBI Add Bus Interface Timing ....................................................................................264
14.3 Receive Link Timing...................................................................................................264
14.4 Transmit Link Timing..................................................................................................265
14.5 Receive APPI Timing (Any-PHY Level 2) ..................................................................265
14.6 Transmit APPI Timing (Any-PHY Level 2) .................................................................268
14.7 Receive APPI Timing (Any-PHY Level 3) ..................................................................271
14.8 Transmit APPI Timing (Any-PHY Level 3) .................................................................272
14.9 Re-Sequencing SDRAM Interface .............................................................................274
14.10 Chunk Buffer SDRAM Interface.................................................................................274
14.11 Context SSRAM Interface (ZBT SSRAM mode) .......................................................275
14.12 Microprocessor Interface ...........................................................................................276
17.1 Power Requirements .................................................................................................280
17.2 Power Sequencing.....................................................................................................280
17.3 Power Supply Filtering...............................................................................................281
FREEDM 84A1024L ASSP Telecom Standard Product Data Sheet
Released
6