PM7311 pmc-sierra, PM7311 Datasheet - Page 269

• Manufacturer Part Number: PM7311
• Description: Freedm 84a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021832, Issue 2
Figure 46 Transmit APPI Timing (Normal Transfer)
Figure 46 shows transfer of a 256 word packet on the Tx APPI for Any-PHY channel 0. The
maximum burst data transfer (excluding channel address prepend) is 128 words, so two data
transfers are required to complete the transfer of the 256 word packet. The start of all burst data
transfers is qualified with the TSX signal and an in-band channel address on TXDATA[15:0] to
associate the data to follow with an Any-PHY channel. The TEOP signal indicates the end of
valid packet data. The TMOD and TERR signals are held low except at the end of a packet
(TEOP set high).
The FREEDM 84A1024L starts driving the TRDY signal one TXCLK cycle after TSX is sampled
high. Upon sampling the TRDY signal high, the external controller completes the current burst
data transfer. The FREEDM 84A1024L tristates the TRDY signal one TXCLK cycle after it has
been driven high. This is the case for the first burst data transfer in Figure 46. In the second
burst data transfer, the FREEDM 84A1024L drives the TRDY signal low to indicate that the
FIFO in the Tx APPI is full and no further data may be transferred. Upon sampling the TRDY
signal low, the external controller must hold the last valid word of data on TXDATA[15:0]. The
FREEDM 84A1024L may drive TRDY low for an indeterminate number of TXCLK cycles.
During this time, the external controller must wait and is not permitted to begin another burst data
transfer until TRDY is sampled high. When there is space in the Tx APPI FIFO, the FREEDM
84A1024L drives the TRDY signal high. Upon sampling the TRDY signal high, the external
controller completes the current burst data transfer. The FREEDM 84A1024L tristates the TRDY
signal one TXCLK cycle after it has been driven high.
The external controller must sample the TRDY signal high and must then wait one clock cycle
before it can begin the next burst data transfer. This prevents the external controller from
bombarding the FREEDM 84A1024L device with small packets and allows the FREEDM
84A1024L to perform the necessary housekeeping and clean up associated with the ending of
burst data transfers. In addition, the rule that TSX must be a minimum of 4 clock cycles apart
must be adhered to. This protocol also ensures that transitions between burst data transfers do not
require any extra per Any-PHY channel storage, thereby simplifying implementation of both the
external controller and the FREEDM 84A1024L device. Figure 47 illustrates this condition.
TXDATA[15:0]
TXCLK
TMOD
TRDY
TEOP
TERR
TSX
CH 0
D0
D1
D2
FREEDM 84A1024L ASSP Telecom Standard Product Data Sheet
D126 D127 CH 0 D128 D129
D130
D131 D132 D254 D255
Released
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