PM7311 pmc-sierra, PM7311 Datasheet - Page 158

• Manufacturer Part Number: PM7311
• Description: Freedm 84a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021832, Issue 2
Register 0x3B0: THDL Configuration
This register configures all provisioned channels.
Reserved
TSTD
BIT8
The reserved bits must be set low for correct operation of the FREEDM 84A1024L device.
The telecom standard bit (TSTD) controls the bit ordering of the HDLC data transferred on
the transmit APPI. When TSTD is set low, the least significant bit of the each byte on the
transmit APPI bus (AD[0] and AD[8]) is the first HDLC bit transmitted and the most
significant bit of each byte (AD[7] and AD[15]) is the last HDLC bit transmitted (datacom
standard). When TSTD is set high, AD[0] and AD[8] are the last HDLC bit transmitted and
AD[7] and AD[15] are the first HDLC bit transmitted (telecom standard).
The least significant stuff control bit (BIT8) carries the value placed in the least significant bit
of each octet when the HDLC processor is configured (7BIT set high) to stuff the least
significant bit of each octet in the corresponding transmit link (TD[n]). When BIT8 is set
high, the least significant bit (last bit of each octet transmitted) is forced high. When BIT8 is
set low, the least significant bit is forced low. BIT8 is ignored when 7BIT is set low.
Bit
Bit 31
To
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
To
Bit 3
To
Bit 0
Bit 4
R/W
R/W
R/W
R/W
Type
FREEDM 84A1024L ASSP Telecom Standard Product Data Sheet
Function
Unused
BIT8
TSTD
Reserved
Unused
Reserved
Default
X
0
0
0
X
0
Released
158