PM7311 pmc-sierra, PM7311 Datasheet - Page 84

• Manufacturer Part Number: PM7311
• Description: Freedm 84a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021832, Issue 2
10.9.10
Figure 28 Linked List Data Structure of a Datagram
Egress Queue Manager (EQM-12)
Managing the Any-PHY channel status, pushing the status to the TAPI-12, accepting transfer
requests from the partial packet processor and arbitrating between the requests are the key tasks
of the egress queue manager. Segmented datagrams are placed into external memory by the
TFRAG block. The number of data bytes in the chunk is added to the Any-PHY channel size
counter. The size is compared against a threshold. An Any-PHY channel size that exceeds the
threshold will cause the EQM-12 to push a status message to the TAPI-12 indicating the Any-
PHY channel is full and will not be accepting any more frames. The EQM-12 maintains the status
of all 1024 Any-PHY channels including the 42 multi-link bundles and the 1024 HDLC channels.
(For non-multi-link channels, two status bits are maintained, for the high priority queue and low
priority queue respectively.)
The partial packet processor requests chunks, as memory becomes available. The egress queue
manager determines the address of the chunk to be transferred to the partial packet processor. The
EQM-12 updates the HDLC and Any-PHY channel context status and pushes the status of the
Any-PHY channel to the TAPI-12. Any-PHY channel status is determined by comparing the size
of the Any-PHY channel to the Any-PHY channel threshold. The two level feedback mechanism
is used to avoid starvation of the HDLC channels. The thresholds are programmable and support
a number of different bandwidths (DS0, nxDS0, T1, E1, nxT1, nxE1, DS3) and ensure that
starvation is avoided.
CB_DRAMC
The CB_DRAMC controls access to/from the Chunk Buffer SDRAM interface present on
FREEDM 84A1024L. The external SDRAMS provide buffer storage for chunks and addresses
pointing to the chunks. The CB_DRAMC block supports a 48 bit wide SDRAM interface
operating at 100 MHz. Refresh, bank switching, providing precharge and bus management are
Size = 3
Last = False; Full = True
Last = False; Full = True
Last = True; Full = False
Next address pointer
Next address pointer
Next address pointer
Starting Address
FREEDM 84A1024L ASSP Telecom Standard Product Data Sheet
(stored on a per HDLC channel basis)
Address of 1st chunk in Datagram
1st chunk in Datagram
2nd chunk in Datagram
Last chunk in Datagram
Released
84