PM7311 pmc-sierra, PM7311 Datasheet - Page 277

• Manufacturer Part Number: PM7311
• Description: Freedm 84a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021832, Issue 2
between each transfer, there is no turn around cycle. Care must be taken to examine the AC
timing to ensure that there is no bus contention on the AD bus between a read followed by a write
transfer. BTERMB is only asserted when the burst access is 4 cycles long. It is not asserted if the
burst cycle is terminated by BLAST or for non-burst accesses (BURSTB=1).
Figure 60 Read and Write to Burstable Address Space
Figure 61 shows consecutive write operations using the WRDONEB signal without the
READYB. Write operations may only begin when WRDONEB is sampled low by the external
interface. On the first data transfer, the cycle is terminated normally. Subsequent access does not
begin until WRDONEB is sampled low by the external interface. This interface is used when the
external processor is incapable of dealing with wait states during write
Figure 61 Consecutive Write Accesses Using WRDONEB
BTERMB
WRDONEB
BUSPOL
BURSTB
READYB
AD(31:0)
BLAST
BUSPOL
BURSTB
AD[31:0]
ADSB
BCLK
BLAST
CSB
BCLK
WR
CSB
WR
1 2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233343536
1
A
2
3
A
D
4
D0
5
FREEDM 84A1024L ASSP Telecom Standard Product Data Sheet
Burst read, 3 wait cycles, mbtermb used
Burst read, 3 wait cycles, mbtermb used
A
6
7
8
D
9
Burst read, 4 wait cycles, no mbtermb
Burst read, 4 wait cycles, no mbtermb
A
10
D
11
12
A
Burst write, 1 wait cycle, mbterm
Burst write, 1 wait cycle, mbterm
A
13
14
D0
D
15
D1
D
16
D2
Burst read, 3
Burst read, 3
A
17
D2
D
18
Released
277