PM7311 pmc-sierra, PM7311 Datasheet - Page 101

• Manufacturer Part Number: PM7311
• Description: Freedm 84a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021832, Issue 2
Register 0x000: Master Reset and Control
This register provides software reset capability, device ID information and SRAM configuration
setup.
RESET
The RESET bit allows the FREEDM 84A1024L to be reset under software control. If the
RESET bit is a logic one, the entire FREEDM 84A1024L, except the microprocessor
interface, is held in reset. All registers are reset to their default values and some memories
are set to their default values (for specific memory operation refer to memory descriptions).
This bit is not self-clearing. Therefore, a logic zero must be written to bring the FREEDM
84A1024L out of reset. Holding the FREEDM 84A1024L in a reset state places it into a low
power, stand-by mode. A hardware reset clears the RESET bit, thus negating the software
reset.
Note: Unlike the hardware reset input (RSTB), RESET does not force the FREEDM
84A1024L’s microprocessor interface pins tristate. RESET causes all registers to be set to
their default values and forces the APPI outputs tristate.
Bit
Bit 31
To
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R
R
R
R
R
R
R
R
R
R
R
R
FREEDM 84A1024L ASSP Telecom Standard Product Data Sheet
Function
Unused
RESET
SRAMM1
SRAMM0
DTYPE[3]
DTYPE[2]
DTYPE[1]
DTYPE[0]
ID[7]
ID[6]
ID[5]
ID[4]
ID[3]
ID[2]
ID[1]
ID[0]
Default
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Released
101