PM7311 pmc-sierra, PM7311 Datasheet - Page 72

• Manufacturer Part Number: PM7311
• Description: Freedm 84a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021832, Issue 2
Figure 18 Partial Packet Buffer Structure
The partial packet buffer processor is divided into three sections: writer, reader and roamer. The
writer is a time-sliced state machine that writes the HDLC data and status information from the
HDLC processor into a channel FIFO in the packet buffer RAM. The reader transfers HDLC
channel FIFO data from the packet buffer RAM to the downstream fragment builder block
(RFRAG). The roamer is a time-sliced state machine that tracks HDLC channel FIFO buffer
depths and signals the reader to service a particular HDLC channel. If a buffer over-run occurs,
the writer ends the current packet from the HDLC processor in the HDLC channel FIFO with an
overrun flag and ignores the rest of the packet.
The FIFO algorithm of the partial packet buffer processor is based on a programmable per-HDLC
channel transfer size. Instead of tracking the number of full blocks in an HDLC channel FIFO,
the processor tracks the number of transactions. Whenever the partial packet writer fills a
transfer-sized number of blocks or writes an end-of-packet flag to the HDLC channel FIFO, a
transaction is created. Whenever the partial packet reader transmits a transfer-size number of
blocks or an end-of-packet flag to the RFRAG block, a transaction is deleted. Thus, small
packets less than the transfer size will be naturally transferred to the RFRAG block without
having to precisely track the number of full blocks in the HDLC channel FIFO.
The partial packet roamer performs the transaction accounting for all HDLC channel FIFOs. The
roamer increments the transaction count when the writer signals a new transaction and sets a per-
HDLC channel flag to indicate a non-zero transaction count. The roamer searches the flags in a
round-robin fashion to decide for which HDLC channel FIFO to request transfer by the RFRAG
Block 4095
Block 200
Block 0
Block 1
Block 2
Block 3
Partial Packet
Buffer RAM
16 bytes
16 bytes
16 bytes
16 bytes
16 bytes
16 bytes
FREEDM 84A1024L ASSP Telecom Standard Product Data Sheet
Block 4095
Block 200
Block 0
Block 1
Block 2
Block 3
Pointer RAM
Block
0xC8
0x03
0x01
XX
XX
XX
Released
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