PM7311 pmc-sierra, PM7311 Datasheet - Page 260

• Manufacturer Part Number: PM7311
• Description: Freedm 84a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021832, Issue 2
The boundary scan register allows testing of board inter-connectivity. The boundary scan register
consists of a shift register placed in series with device inputs and outputs. Using the boundary
scan register, all digital inputs can be sampled and shifted out on primary output TDO. In
addition, patterns can be shifted in on primary input, TDI and forced onto all digital outputs.
TAP Controller
The TAP controller is a synchronous finite state machine clocked by the rising edge of primary
input, TCK. All state transitions are controlled using primary input, TMS. The finite state
machine is described below.
Figure 36 TAP Controller Finite State Machine
Test-Logic-Reset
The test logic reset state is used to disable the TAP logic when the device is in normal mode
operation. The state is entered asynchronously by asserting input, TRSTB. The state is entered
synchronously regardless of the current TAP controller state by forcing input, TMS high for 5
TCK clock cycles. While in this state, the instruction register is set to the IDCODE instruction.
0
1
Test-Logic-Reset
Run-Test-Idle
TRSTB=0
0
1
FREEDM 84A1024L ASSP Telecom Standard Product Data Sheet
1
0
Select-DR-Scan
Capture-DR
Update-DR
Pause-DR
Exit1-DR
Exit2-DR
Shift-DR
1
1
1
0
0
0
1
0
All transitions dependent on input TMS
0
0
1
1
1
0
Select-IR-Scan
Capture-IR
Update-IR
Pause-IR
Exit1-IR
Exit2-IR
Shift-IR
1
1
1
0
0
0
1
0
0
0
1
1
Released
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