PM7311 pmc-sierra, PM7311 Datasheet - Page 272

• Manufacturer Part Number: PM7311
• Description: Freedm 84a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021832, Issue 2
14.8 Transmit APPI Timing (Any-PHY Level 3)
The transmit Any-PHY packet interface (APPI) timing is shown in Figure 50 through Figure 52.
An external controller provides data to the FREEDM 84A1024L device using the transmit APPI.
The following discussion surrounding the transmit APPI functional timing assumes that point to
point interfaces exist between FREEDM 84A1024L and the external controller. The FREEDM
84A1024L compares the TXADDR[15:0] to the base and range address registers to determine if
the address is destined for the FREEDM 84A1024L.
Figure 50 Transmit APPI Timing Any-PHY Level 3 (Normal Transfer)
Figure 50 shows transfer of a 254 byte packet on the Tx APPI of FREEDM 84A1024L. The start
of all burst data transfers is qualified with the TSX signal and an in-band Any-PHY channel
address on TXDATA[7:0] to associate the data to follow with an Any-PHY channel. The TEOP
signal indicates the end of valid packet data. The TERR signal is held low except at the end of a
packet (TEOP set high).
The TRDY signal is valid one TXCLK cycle after TSX is sampled high. Upon sampling the
TRDY signal high, the external controller completes the current burst data transfer. This is the
case for the first burst data transfer in Figure 50. In Figure 51, the FREEDM 84A1024L drives
the TRDY signal low to indicate that the FIFO in the Tx APPI are full and no further data may be
transferred. Upon sampling the TRDY signal low, the external controller must hold the last valid
word of data on TXDATA[7:0]. The FREEDM 84A1024L may drive TRDY low for an
indeterminate number of TXCLK cycles. During this time, the external controller must wait and
is not permitted to begin another burst data transfer until TRDY is sampled high. Upon sampling
the TRDY signal high, the external controller completes the current burst data transfer.
The external controller can sample the TRDY signal high before it can begin the next burst data
transfer. TRDY is provided to prevent the external controller from bombarding the FREEDM
84A1024L device with small packets and allows the FREEDM 84A1024L to perform the
necessary housekeeping and clean up associated with the ending of burst data transfers. In
addition, the rule that TSX must be a minimum of 4 clock cycles apart must be adhered. This
protocol also ensures that transitions between burst data transfers do not require any extra per
Any-PHY channel storage, thereby simplifying implementation of both the external controller
and the FREEDM 84A1024L device. Figure 51 illustrates this condition.
TXDATA[7:0]
TXPRTY
TXCLK
TRDY
TEOP
TERR
TSX
CH 0 CH 0 CI 1
CI 2
FREEDM 84A1024L ASSP Telecom Standard Product Data Sheet
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11 D252 D253
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