PM7311 pmc-sierra, PM7311 Datasheet - Page 266

• Manufacturer Part Number: PM7311
• Description: Freedm 84a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021832, Issue 2
The data transfer begins when the external controller selects FREEDM 84A1024L device 0 by
placing that address on the RXADDR[3:0] inputs and setting RENB high. The external controller
sets RENB low in the next RXCLK cycle to commence data transfer across the Rx APPI. The
FREEDM 84A1024L samples RENB low and responds by asserting RSX one RXCLK cycle
later. The start of all burst data transfers is qualified with RSX and an in-band Any-PHY channel
address on RXDATA[15:0] to associate the data to follow with an Any-PHY channel.
During the cycle when D2 is placed on RXDATA[15:0], the external controller is unable to accept
any further data and sets RENB high. Two RXCLK cycles later, the FREEDM 84A1024L
tristates the Rx APPI. The external controller may hold RENB high for an indeterminate number
of RXCLK cycles. The FREEDM 84A1024L will wait until the external controller returns RENB
low. Because the FREEDM 84A1024L does not support interrupted data transfers on the Rx
APPI, the external controller must reselect FREEDM 84A1024L device 0 or output a null address
during the clock cycle before it returns RENB low. However, while RENB remains high, the
address on the RXADDR[3:0] signals may change. When the FREEDM 84A1024L device 0
samples RENB low, it continues data transfer by providing D4 on RXDATA[15:0]. Note that if
D3 were the final word of the packet (Status), in response to sampling REOP high, the external
controller does not have to reselect FREEDM 84A1024L device 0. This is shown in Figure 45.
The FREEDM 84A1024L will not pause burst data transfers across the Rx APPI.
The FREEDM 84A1024L automatically deselects at the end of all burst data transfers. The
FREEDM 84A1024L must be reselected before any further data will be transferred across the Rx
APPI.
The RVAL and REOP signals indicate the presence and end of valid packet data respectively. The
RERR and RMOD signals are only valid at the end of a packet and are qualified with the REOP
signal. When a packet is erred, the FREEDM 84A1024L may be programmed to overwrite
RXDATA[15:0] in the final word of packet transfer with status information indicating the cause
of the error. RXDATA[15:0] is not modified if a packet is error free.
The RXADDR[3:0] signals serve to poll FREEDM 84A1024L devices as well as for selection.
During data transfer, the RXADDR[3:0] signals continue to poll the FREEDM 84A1024L
devices sharing the Rx APPI. Polled results are returned on the RPA signal. Note that each poll
address is separated by a NULL address to generate tristate turn-around cycle in order to prevent
multiple FREEDM 84A1024L devices from briefly driving RPA. If RPA is a point-to-point signal
for each FREEDM 84A1024L device on the board, then the tristate turn-around cycle is not
required, thereby effectively doubling the polling bandwidth at the expense of extra signals.
Polled results reflect the status of the Rx APPI. Polled responses always refer to the next segment
transfer. In other words, polled responses during or after the RXCLK cycle where RSX is set
high refer to a segment that is not involved in the current data transfer. This allows the external
controller to gather knowledge about the segment not involved in the current segment transfer so
that it can anticipate reselecting that FREEDM 84A1024L device (via RENB) to maximize
bandwidth on the Rx APPI (shown in Figure 44).
FREEDM 84A1024L ASSP Telecom Standard Product Data Sheet
Released
266