PM7311 pmc-sierra, PM7311 Datasheet - Page 70

• Manufacturer Part Number: PM7311
• Description: Freedm 84a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021832, Issue 2
10.9.3
associate the link and time-slot identity with an HDLC channel. The position of T1/J1 and E1
framing bits/bytes is identified by frame pulse signals generated by the EXSBI. Links containing
a DS3 stream are unchannelized, i.e. all data on the link belongs to one HDLC channel. The
RCAS-12 performs a table lookup using only the link number to determine the associated HDLC
channel, as time-slots are non-existent in unchannelized links. Links may additionally be
configured to operate in an unframed “clear channel” mode, in which all bit positions, including
those normally reserved for framing information, are assumed to be carrying HDLC data. Links
so configured operate as unchannelized regardless of link rate and the RCAS-12 performs a table
lookup using only the link number to determine the associated HDLC channel.
All timeslots in a link must be provisioned to a valid channel number before the link is enabled.
For unused timeslots, a valid unused channel number must be set but the PROV bit is not set. All
unused timeslots in the device can be mapped to the same unused channel number. When
unprovisioning a channel, the INVERT bit in register 0x208 must be cleared (if set), The PROV
bit is then set to 0 but the channel number must be written back into the channel number field.
This will flush out any data on this channel still present in the chip. This sequence must occur
before the link is disabled.
The loop back controller block implements the channel based diagnostic loop back function.
Every valid data byte belonging to a channel with diagnostic loop back enabled from the Transmit
HDLC Processor / Partial Packet Buffer block (THDL-12) is written into a 1024 word FIFO. The
loop back controller monitors for an idle time-slot or a time-slot carrying a channel with
diagnostic loop back enabled. If either condition holds, the current data byte is replaced by data
retrieved from the loop back data FIFO.
Receive HDLC Protocol Engine (RHDL-12)
The HDLC engine receives the incoming byte stream and examines the stream to determine the
opening and closing of the HDLC packet. Bit de-stuffing, FCS checking and
minimum/maximum packet size checking is performed. The HDLC engine is capable of
simultaneously processing 1024 independent HDLC channels. The resulting HDLC data and
status information is passed to the Partial Packet Processor to be stored in the appropriate HDLC
channel FIFO buffer.
Figure 16 shows a diagram of the synchronous HDLC protocol supported by the FREEDM
84A1024L device. The incoming stream is examined for flag bytes (01111110 bit pattern) that
delineate the opening and closing of the HDLC packet. The packet is bit de-stuffed which
discards a “0” bit which directly follows five contiguous “1” bits. The resulting HDLC packet
size must be a multiple of an octet (8 bits) and within the expected minimum and maximum
packet length limits. The minimum packet length is that of a packet containing two information
bytes (address and control) and FCS bytes. For packets with CRC-CCITT as FCS, the minimum
packet length is four bytes while those with CRC-32 as FCS; the minimum length is six bytes.
An HDLC packet is aborted when seven contiguous “1” bits (with no inserted “0” bits) are
received. At least one flag byte must exist between HDLC packets for delineation. Contiguous
flag bytes, or all ones bytes between packets are used as an “inter-frame time fill”. Adjacent flag
bytes may share zeros.
FREEDM 84A1024L ASSP Telecom Standard Product Data Sheet
Released
70