SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 888

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

47.2.10
47.2.10.1
47.2.11
47.2.11.1
47.2.12
47.2.12.1
47.2.12.2
888
AT91SAM9R64/RL64
System Controller
TSADCC
USART
Possible event loss when reading RTT_SR
TSADCC: Multiple PENCNT detections without NOCNT
USART: RXBREAK problem when no timeguard
USART: DCD is active High instead of Low
If an event (RTTINC or ALMS) occurs within the same slow clock cycle the RTT_SR is read, the
corresponding bit might be cleared. This might lead in the loss of this event.
The software must handle RTT event as interrupt and should not poll RTT_SR.
In addition to the "Pen Contact" bit (PENCNT), the TSADCC provides a "No Contact" bit
(NOCNT) in its Status Register. When a contact loss is detected by the analog block of the
peripheral, an internal debouncer is started. However, if the contact loss is not validated by the
debouncer (e.g. if it was a glitch), the PENCNT flag is incorrectly set again in the Status Regis-
ter. This results in the PENCNT flag being set multiple times before NOCNT is set.
The user must disregard the value of the PENCNT flag after it has been set once and before the
NOCNT flag has been set. When using interrupts, the interrupt on PENCNT must be disabled
after it has occurred once, and re-enabled when NOCNT occurs.
The RXBREAK flag is not correctly handled (FRAME ERROR is set instead) when the time-
guard is 0 and the break character is located just after STOP BIT.
If the NBSTOP = 1, => TIMEGUARD should be different from 0.
SYNCHRONOUS mode is not affected, only ASYNCHRONOUS.
DCD signal is active at high level in the USART block (Modem Mode).
DCD should be active at low level.
Add an inverter.
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
6289D–ATARM–3-Oct-11