SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 862

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Table 44-27. SMC Read Signals - NCS Controlled (Read_MODE = 0) (Continued)
44.8.5.2
Table 44-28. SMC Write Signals - NWE controlled (WRITE_MODE = 1)
Note:
862
Symbol
SMC
SMC
SMC
SMC
SMC
Symbol
SMC
SMC
SMC
SMC
SMC
SMC
SMC
10
11
12
13
14
15
16
17
18
19
20
21
1. hold length = total cycle duration - setup duration - pulse duration. “hold length” is for “ncs wr hold length” or “NWE hold
AT91SAM9R64/RL64
length”.
Write Timings
Parameter
Data Out Valid before NWE High
NWE Pulse Width
NBS0/A0 NBS1, NBS2/A1, NBS3, A2 - A25
valid before NWE low
NCS low before NWE high
NWE High to Data OUT, NBS0/A0 NBS1,
NBS2/A1, NBS3, A2 - A25 change
NWE High to NCS Inactive
NWE High to Data OUT, NBS0/A0 NBS1,
NBS2/A1, NBS3, A2 - A25, NCS change
Parameter
VDDIOM supply
Data Setup before NCS High
Data Hold after NCS High
NBS3, A2 - A25 valid before
NCS High
NRD low before NCS High
NCS Pulse Width
NBS0/A0, NBS1, NBS2/A1,
HOLD or NO HOLD SETTINGS (ncs rd hold ≠ 0, ncs rd hold = 0)
HOLD or NO HOLD SETTINGS (nwe hold ≠ 0, nwe hold = 0)
(1)
NO HOLD SETTINGS (nwe hold = 0)
HOLD SETTINGS (ncs rd hold ≠ 0)
HOLD SETTINGS (nwe hold ≠ 0)
(ncs rd setup + ncs rd pulse)* t
(ncs rd setup + ncs rd pulse - nrd
ncs rd pulse length * t
(1)
setup)* t
(nwe setup - ncs rd setup +
(nwe hold - ncs wr hold)*
nwe pulse) * t
nwe pulse * t
nwe pulse * t
nwe setup * t
nwe hold * t
1.8V
- 5.1
9.8
CPMCK
0
1.8V Supply
t
CPMCK
- 2.4
CPMCK
5.8
CPMCK
CPMCK
CPMCK
Min in MAX corner
CPMCK
- 3.0
CPMCK
- 1.1
CPMCK
Min in MAX corner
- 3.5
- 2.2
- 0.4
- 2.9
- 2.5
(ncs rd setup + ncs rd pulse - nrd
ncs rd pulse length * t
(ncs rd setup + ncs rd pulse)*
(nwe setup - ncs rd setup +
(nwe hold - ncs wr hold)*
nwe pulse) * t
nwe setup * t
nwe pulse * t
nwe pulse * t
nwe hold * t
setup)* t
3.3V Supply
t
t
CPMCK
CPMCK
3.3V
10.0
CPMCK
7.2
0
- 4.8
CPMCK
CPMCK
CPMCK
CPMCK
- 2.8
CPMCK
- 2.1
CPMCK
- 3.2
6289D–ATARM–3-Oct-11
- 3.4
- 9.9
- 4.4
- 3.9
- 1.1
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns