SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 596

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

37.5
Table 37-2.
6289D–ATARM–3-Oct-11
Offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
0x034
0x038
0x03C
0x040
0x044
0x048
0x04C
0x050
0x054
0x058
0x05C
0x060
0x064
0x068
0x06C
0x070
0x074
DMA Controller (DMAC) User Interface
Register Mapping
Register
DMAC Global Configuration Register
DMAC Enable Register
Reserved
Reserved
Reserved
Reserved
DMAC Error, Chained Buffer transfer completed and
Buffer transfer completed Interrupt Enable register.
DMAC Error, Chained Buffer transfer completed and
Buffer transfer completed Interrupt Disable register.
DMAC Error, Chained Buffer transfer completed and
Buffer transfer completed Mask Register.
DMAC Error, Chained Buffer transfer completed and
Buffer transfer completed Status Register.
DMAC Channel Handler Enable Register
DMAC Channel Handler Disable Register
DMAC Channel Handler Status Register
Reserved
Reserved
DMAC Channel 0 Source Address Register
DMAC Channel 0 Destination Address Register
DMAC Channel 0 Descriptor Address Register
DMAC Channel 0 Control A Register
DMAC Channel 0 Control B Register
DMAC Channel 0 Configuration Register
DMAC Channel 0 Source Picture in Picture
Configuration Register
DMAC Channel 0 Destination Picture in Picture
Configuration Register
Reserved
Reserved
DMAC Channel 1 Source Address Register
DMAC Channel 1 Destination Address Register
DMAC Channel 1 Descriptor Address Register
DMAC Channel 1 Control A Register
DMAC Channel 1 Control B Register
Name
DMAC_GCFG
DMAC_EN
DMAC_EBCIER
DMAC_EBCIDR
DMAC_EBCIMR
DMAC_EBCISR
DMAC_CHER
DMAC_CHDR
DMAC_CHSR
DMAC_SADDR0
DMAC_DADDR0
DMAC_DSCR0
DMAC_CTRLA0
DMAC_CTRLB0
DMAC_CFG0
DMAC_SPIP0
DMAC_DPIP0
DMAC_SADDR1
DMAC_DADDR1
DMAC_DSCR1
DMAC_CTRLA1
DMAC_CTRLB1
–
–
–
–
–
–
–
–
AT91SAM9R64/RL64
Access
Read/Write
Read/Write
Write-only
Write-only
Read-only
Read-only
Write-only
Read-only
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Write-only
–
–
–
–
–
–
–
–
Reset State
0x10
0x0
0x0
0x0
0x00FF0000
0x0
0x0
0x0
0x0
0x0
0x01000000
0x0
0x0
0x0
0x0
0x0
0x0
0x0
–
–
–
–
–
–
–
–
–
–
–
–
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