SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 147

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SAM9RL64

Manufacturer Part Number
SAM9RL64
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM9RL64

Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
118
Ext Interrupts
118
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
5
Ssc
2
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
6
Adc Resolution (bits)
10
Adc Speed (ksps)
220
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
21.6.1
21.6.2
21.6.3
21.6.4
21.6.5
21.6.6
6289D–ATARM–3-Oct-11
Bus Multiplexing
Pull-up Control
Static Memory Controller
SDRAM Controller
ECC Controller
CompactFlash Support
The EBI and EBI1 offers a complete set of control signals that share the 32-bit data lines, the
address lines of up to 26 bits and the control signals through a multiplex logic operating in func-
tion of the memory area requests.
Multiplexing is specifically organized in order to guarantee the maintenance of the address and
output control lines at a stable state while no external access is being performed. Multiplexing is
also designed to respect the data float times defined in the Memory Controllers. Furthermore,
refresh cycles of the SDRAM are executed independently by the SDRAM Controller without
delaying the other external Memory Controller accesses.
The EBI_CSA register in the Chip Configuration User Interface permit enabling of on-chip pull-
up resistors on the data bus lines not multiplexed with the PIO Controller lines. The pull-up resis-
tors are enabled after reset. Setting the EBI_DBPUC bit disables the pull-up resistors on the D0
to D15 lines. Enabling the pull-up resistor on the D16-D31 lines can be performed by program-
ming the appropriate PIO controller.
For information on the Static Memory Controller, refer to the Static Memory Controller section.
For information on the SDRAM Controller, refer to the SDRAM section.
For information on the ECC Controller, refer to the ECC section.
The External Bus Interface integrates circuitry that interfaces to CompactFlash devices.
The CompactFlash logic is driven by the Static Memory Controller (SMC) on the NCS4 and/or
NCS5 address space. Programming the EBI_CS4A and/or EBI_CS5A bit of the EBI_CSA Reg-
ister in the Chip Configuration User Interface to the appropriate value enables this logic. For
details on this register, refer to the in the Bus Matrix Section. Access to an external Compact-
Flash device is then made by accessing the address space reserved to NCS4 and/or NCS5 (i.e.,
between 0x5000 0000 and 0x5FFF FFFF for NCS4 and between 0x6000 0000 and 0x6FFF
FFFF for NCS5).
All CompactFlash modes (Attribute Memory, Common Memory, I/O and True IDE) are sup-
ported but the signals _IOIS16 (I/O and True IDE modes) and _ATA SEL (True IDE mode) are
not handled.
• the ECC Controller (ECC)
• a chip select assignment feature that assigns an AHB address space to the external devices
• a multiplex controller circuit that shares the pins between the different Memory Controllers
• programmable CompactFlash support logic
• programmable NAND Flash support logic
AT91SAM9R64/RL64
147

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