SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 433

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

33.10.6
Name:
Access:
Reset Value: 0x0000F009
• TXCOMP: Transmission Completed (automatically set / reset)
TXCOMP used in Master mode:
0 = During the length of the current frame.
1 = When both holding and shifter registers are empty and STOP condition has been sent.
TXCOMP behavior in Master mode can be seen in
TXCOMP used in Slave mode:
0 = As soon as a Start is detected.
1 = After a Stop or a Repeated Start + an address different from SADR is detected.
TXCOMP behavior in Slave mode can be seen in
page 424
• RXRDY: Receive Holding Register Ready (automatically set / reset)
0 = No character has been received since the last TWI_RHR read operation.
1 = A byte has been received in the TWI_RHR since the last read.
RXRDY behavior in Master mode can be seen in
RXRDY behavior in Slave mode can be seen in
page 424
• TXRDY: Transmit Holding Register Ready (automatically set / reset)
TXRDY used in Master mode:
0 = The transmit holding register has not been transferred into shift register. Set to 0 when writing into TWI_THR register.
1 = As soon as a data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at
the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI).
TXRDY behavior in Master mode can be seen in
433
TXBUFE
31
23
15
–
–
7
–
AT91SAM9R64/RL64
and
and
TWI Status Register
TWI_SR
Read-only
Figure 33-30 on page
Figure 33-30 on page
RXBUFF
OVRE
30
22
14
–
–
6
ENDTX
GACC
424.
424.
29
21
13
–
–
5
Figure 33-8 on page
Figure 33-10 on page
Figure 33-25 on page
ENDRX
SVACC
Figure 33-27 on page
Figure 33-8 on page 404
28
20
12
–
–
4
EOSACC
SVREAD
27
19
11
–
–
3
404.
405.
420,
422,
and in
Figure 33-28 on page
Figure 33-28 on page
SCLWS
TXRDY
26
18
10
Figure 33-10 on page
–
–
2
ARBLST
RXRDY
25
17
–
–
9
1
423,
423,
6289D–ATARM–3-Oct-11
405.
Figure 33-29 on
Figure 33-29 on
TXCOMP
NACK
24
16
–
–
8
0