SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 551

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

36.6
Table 36-4.
Table 36-5.
Notes:
6289D–ATARM–3-Oct-11
Offset
0xC0
0xC4
Offset
0x00
0x40
0x80
0x0C
0x1C
0x2C
0x00
0x04
0x08
0x10
0x14
0x18
0x20
0x24
0x28
0xFC
Timer Counter (TC) User Interface
1. Read-only if WAVE = 0
Channel/Register
TC Channel 0
TC Channel 1
TC Channel 2
TC Block Control Register
TC Block Mode Register
TC Global Memory Map
TC Channel Memory Map
Register
Channel Control Register
Channel Mode Register
Reserved
Reserved
Counter Value
Register A
Register B
Register C
Status Register
Interrupt Enable Register
Interrupt Disable Register
Interrupt Mask Register
Reserved
TC_BCR (Block Control Register) and TC_BMR (Block Mode Register) control the whole TC
block. TC channels are controlled by the registers listed in
channel registers in
tioned in
Table 36-5
.
Table 36-5
is in relation to the offset of the corresponding channel as men-
TC_CMR
TC_CCR
TC_IMR
TC_IER
TC_IDR
TC_CV
TC_RA
TC_RB
TC_RC
TC_SR
TC_BCR
TC_BMR
Name
Name
–
See
See
See
Read/Write
Read/Write
AT91SAM9R64/RL64
Read/Write
Read/Write
Read/Write
Write-only
Read-only
Read-only
Write-only
Write-only
Read-only
Write-only
Access
Access
Table 36-5
Table 36-5
Table 36-5
Table 36-5
–
(1)
(1)
. The offset of each of the
Reset Value
Reset Value
–
0
–
–
0
0
0
0
0
–
–
0
–
–
0
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