SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 883

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

47.2.3.2
47.2.3.3
47.2.4
47.2.4.1
6289D–ATARM–3-Oct-11
MCI
LCD Periodic Bad Pixels
24-bit Packed Mode
MCI: Busy signal of R1b responses is not taken in account
LCD periodic bad pixels is due to mis-aligned DMA base address in frame buffer. LCD DMA per-
forms bursts to read memory. These bursts must not cross 1 Kb AMBA boundary.
The burst size in 32-bit words is programmed by field BRSTLN in DMA_FRMCFG register.
The LCD DMA Base Address is programmed in DMA_BADDR1 register.
DMA Base Address must be programmed with a value aligned onto LCD DMA burst size.
e.g.:
BRSTLN = 15
For a 16-word burst, the LCD DMA Base Address must start on 16-word offset: 0x0, 0x40, 0x80
or 0xc0.
BRSTLN = 3
For a 4-word burst, the LCD DMA Base Address must start on 0x0, 0x10, ..., 0xf0.
LCD DMA Base Address and LCD DMA burst size must be selected with care in 24-bit packed
mode. A 32-bit word contains some bits of a pixel and some bits of the following. If LCD DMA
Base Address is not aligned with a pixel start, the colors will be modified.
Respect "LCD periodic bad pixels" erratum constrains lead to select the LCD DMA Base
Address regarding the LCD DMA burst size.
LCD DMA Base Address is to be set on a pixel start, every three 32-bit word.
The offset of the LCD DMA Base Address must be a multiple of 0x30 plus 0x0, 0xc, 0x18 or
0x24. (0x0, 0xc, 0x18, 0x24, 0x30, 0x3c, 0x48, 0x54, 0x60,0x6c, 0x78, 0x84, 0x90, 0x9c, 0xa8,
0xb4, 0xc0 ...)
e.g. regarding the bursts size:
1) BRSTLN = 3 implies the following LCD DMA Base Address offsets: 0x0, 0x30, 0x60, ...
2) BRSTLN = 15 implies the following LCD DMA Base Address offsets: 0x0 and 0xc0 only
The busy status of the card during the response (R1b) is ignored for the commands CMD7,
CMD28, CMD29, CMD38, CMD42, CMD56. Additionally, for commands CMD42 and CMD56 a
• LCD power off
• DMA disable
• Wait for DMABUSY
• DMA reset
• LCD power on
• DMA enable.
Problem Fix/Workaround
Problem Fix/Workaround
AT91SAM9R64/RL64
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