SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 587

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Figure 37-11. DMAC Transfer Flow for Replay Mode at Source and Linked List Destination Address
37.3.4.6
6289D–ATARM–3-Oct-11
Multi-buffer Transfer with Source Address Auto-reloaded and Contiguous Destination Address (Row 11)
HDMA Transfer Complete
interrupt generated here
1. Read the Channel Enable register to choose a free (disabled) channel.
2. Clear any pending interrupts on the channel from the previous DMAC transfer by read-
3. Program the following channel registers:
ing to the Interrupt Status Register.
a. Write the starting source address in the DMAC_SADDRx register for channel x.
b. Write the starting destination address in the DMAC_DADDRx register for channel
c. Program DMAC_CTRLAx, DMAC_CTRLBx and DMAC_CFGx according to Row
d. Write the control information for the DMAC transfer in the DMAC_CTRLBx and
– Set up the transfer characteristics, such as:
– Transfer width for the source in the SRC_WIDTH field.
– Transfer width for the destination in the DST_WIDTH field.
x.
11 as shown in
‘0’. DMAC_CTRLBx.AUTO field is set to ‘1’ to enable automatic mode support.
DMAC_CTRLAx register for channel x. For example, in this register, you can pro-
gram the following:
Buffer Complete interrupt
generated here
Channel Disabled by
hardware
Table 37-1 on page
yes
DADDRx, CTRLAx, CTRLBx, DSCRx
HDMA State Machine Table?
status information in LLI
Hardware reprograms
Writeback of control
Channel Enabled by
DMA buffer transfer
Reload SADDRx
Is HDMA in
575. Program the DMAC_DSCRx register with
LLI Fetch
Row1 of
software
no
AT91SAM9R64/RL64
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