SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 292
SAM9RL64
Manufacturer Part Number
SAM9RL64
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9260.pdf
(290 pages)
3.SAM9261.pdf
(248 pages)
4.SAM9R64.pdf
(903 pages)
5.SAM9R64.pdf
(52 pages)
Specifications of SAM9RL64
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
118
Ext Interrupts
118
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
5
Ssc
2
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
6
Adc Resolution (bits)
10
Adc Speed (ksps)
220
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- SAM9260 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9R64 PDF datasheet #4
- SAM9R64 PDF datasheet #5
- Current page: 292 of 903
- Download datasheet (13Mb)
28.5.1
Register Name:
Access Type:
• ULBT: Undefined Length Burst Type
0: Infinite Length Burst
No predicted end of burst is generated and therefore INCR bursts coming from this master cannot be broken.
1: Single Access
The undefined length burst is treated as a succession of single accesses, allowing rearbitration at each beat of the INCR
burst.
2: Four-beat Burst
The undefined length burst is split into four-beat burst allowing rearbitration at each four-beat burst end.
3: Eight-beat Burst
The undefined length burst is split into eight-beat burst allowing rearbitration at each eight-beat burst end.
4: Sixteen-beat Burst
The undefined length burst is split into sixteen-beat burst allowing rearbitration at each sixteen-beat burst end.
6289D–ATARM–3-Oct-11
31
23
15
–
–
–
7
–
Bus Matrix Master Configuration Registers
30
22
14
MATRIX_MCFG0...MATRIX_MCFG5
Read/Write
–
–
–
6
–
29
21
13
–
–
–
5
–
28
20
12
–
–
–
4
–
27
19
11
–
–
–
3
–
AT91SAM9R64/RL64
26
18
10
–
–
–
2
ULBT
25
17
–
–
9
–
1
24
16
–
–
8
–
0
292
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