SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 760

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

41.5
Table 41-5.
Notes:
760
0x00
0x04
0x08 - 0x0C
0x10
0x14
0x18
0x1C
0x20 - 0xCC
0xE0
0xE4 - 0xE8
0xEC
0xF0
0xF4
0xF8
0x100
0x104
0x108
0x10C
0x110
0x114
0x118
0x11C
0x120 - 0x1DC
0x300 - 0x30C
0x310
0x314
0x318
0x31C
0x320 - 0x370
Offset
USB High Speed Device Port (UDPHS) User Interface
1. The reset value for UDPHS_EPTCTL0 is 0x0000_0001.
2. The addresses for the UDPHS Endpoint registers shown here are for UDPHS Endpoint0. The structure of this group of reg-
3. The addresses for the UDPHS DMA registers shown here are for UDPHS DMA Channel1. (There is no Channel0) The
AT91SAM9R64/RL64
isters is repeated successively for each endpoint according to the consecution of endpoint registers located between 0x120
and
structure of this group of registers is repeated successively for each DMA channel according to the consecution of DMA reg-
isters located between 0x320 and 0x370.
Register Mapping
0x1DC
Register
UDPHS Control Register
UDPHS Frame Number Register
Reserved
UDPHS Interrupt Enable Register
UDPHS Interrupt Status Register
UDPHS Clear Interrupt Register
UDPHS Endpoints Reset Register
Reserved
UDPHS Test Register
Reserved
UDPHS PADDRSIZE Register
UDPHS Name1 Register
UDPHS Name2 Register
UDPHS Features Register
UDPHS Endpoint0 Configuration Register
UDPHS Endpoint0 Control Enable Register
UDPHS Endpoint0 Control Disable Register
UDPHS Endpoint0 Control Register
Reserved (for endpoint 0)
UDPHS Endpoint0 Set Status Register
UDPHS Endpoint0 Clear Status Register
UDPHS Endpoint0 Status Register
UDPHS Endpoint1 to 6
Reserved
UDPHS DMA Next Descriptor1 Address Register
UDPHS DMA Channel1 Address Register
UDPHS DMA Channel1 Control Register
UDPHS DMA Channel1 Status Register
DMA Channel2 to 5
.
(3)
Registers
(2)
Registers
UDPHS_CTRL
UDPHS_FNUM
–
UDPHS_IEN
UDPHS_INTSTA
UDPHS_CLRINT
UDPHS_EPTRST
–
UDPHS_TST
–
UDPHS_IPPADDRSIZE
UDPHS_IPNAME1
UDPHS_IPNAME2
UDPHS_IPFEATURES
UDPHS_EPTCFG0
UDPHS_EPTCTLENB0
UDPHS_EPTCTLDIS0
UDPHS_EPTCTL0
–
UDPHS_EPTSETSTA0
UDPHS_EPTCLRSTA0
UDPHS_EPTSTA0
–
UDPHS_DMANXTDSC1
UDPHS_DMAADDRESS1
UDPHS_DMACONTROL1
UDPHS_DMASTATUS1
Name
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Access
Read
Read
Read
Read
Read
Read
Write
Read
Read
Write
Write
Write
Write
Write
–
–
–
–
–
6289D–ATARM–3-Oct-11
0x0000_0000
0x0000_0200
0x0000_0000
0x0000_0010
0x0000_0000
0x0000_0000
0x0000_4000
0x4855_5342
0x3244_4556
0x0000_0000
0x0000_0040
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
–
–
–
–
–
–
–
–
–
–
–
(1)