SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 576

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

37.3.3.6
37.3.3.7
6289D–ATARM–3-Oct-11
Suspension of Transfers Between buffers
Ending Multi-buffer Transfers
b u f f e r s i s a f u n c t i o n o f D M A C _ C T R L A x . S R C _ D S C R , D M A C _ C F G x . S R C _ R E P ,
DMAC_CTRLAx.DST_DSCR and DMAC_CFGx.DST_REP registers.
At the end of every buffer transfer, an end of buffer interrupt is asserted if:
Note:
At the end of a chain of multiple buffers, an end of linked list interrupt is asserted if:
All multi-buffer transfers must end as shown in Row 1 of
every buffer transfer, the DMAC samples the row number, and if the DMAC is in Row 1 state,
then the previous buffer transferred was the last buffer and the DMAC transfer is terminated.
F o r r o w s 9 , 1 0 a n d 1 1 o f
DMAC_CTRLBx.AUTO is set), multi-buffer DMAC transfers continue until the automatic mode is
disabled by writing a ‘1’ in DMAC_CTRLBx.AUTO bit. This bit should be programmed to zero in
the end of buffer interrupt service routine that services the next-to-last buffer transfer. This puts
the DMAC into Row 1 state.
For rows 2, 3, 4, 5, and 6 (DMAC_CRTLBx.AUTO cleared) the user must setup the last buffer
d e s c r i p t o r i n m e m o r y s u c h t h a t b o t h L L I . D M A C _ C T R L B x . S R C _ D S C R a n d
LLI.DMAC_CTRLBx.DST_DSCR are one and LLI.DMAC_DSCRx is set to 0.
• the channel buffer interrupt is unmasked, DMAC_EBCIMR.BTC[n] = ‘1’, where n is the
• the channel end of chained buffer interrupt is unmasked, DMAC_EBCIMR.CBTC[n] = ‘1’,
channel number.
when n is the channel number.
The buffer complete interrupt is generated at the completion of the buffer transfer to the
destination.
T a b l e 3 7 - 1 o n p a g e 5 7 5
AT91SAM9R64/RL64
Table 37-1 on page
, ( D M A C _ D S C R x = 0 a n d
575. At the end of
576