SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 50

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SAM9RL64

Manufacturer Part Number
SAM9RL64
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM9RL64

Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
118
Ext Interrupts
118
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
5
Ssc
2
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
6
Adc Resolution (bits)
10
Adc Speed (ksps)
220
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
12.2
Figure 12-1. ARM926EJ-S Internal Functional Block Diagram
12.3
12.3.1
12.3.2
50
Block Diagram
ARM9EJ-S Processor
AT91SAM9R64/RL64
ARM9EJ-S Operating States
Switching State
Interface
ICE
EmbeddedICE
WDATA
-RT
Interface
ARM9EJ-S
ETM
The ARM9EJ-S processor can operate in three different states, each with a specific instruction
set:
In Jazelle state, all instruction Fetches are in words.
The operating state of the ARM9EJ-S core can be switched between:
• ARM state: 32-bit, word-aligned ARM instructions.
• THUMB state: 16-bit, halfword-aligned Thumb instructions.
• Jazelle state: variable length, byte-aligned Jazelle instructions.
• ARM state and THUMB state using the BX and BLX instructions, and loads to the PC
Processor
RDATA
INSTR
Coprocessor
DA
Interface
IA
Droute
Iroute
ARM926EJ-S
DCACHE
DEXT
MMU
ICACHE
IEXT
Interface
Interface
TCM
Instruction
Bus
Unit
Interface
Interface
AHB
Data
AHB
AHB
AHB
6289D–ATARM–3-Oct-11

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