SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 54

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

12.3.7.2
54
Exception Types and Priorities
AT91SAM9R64/RL64
Exceptions
Figure 12-2. Status Register Format
Figure 12-2
The
leged mode. The types of exceptions are:
When an exception occurs, the banked version of R14 and the SPSR for the exception mode
are used to save the state.
More than one exception can happen at a time, therefore the ARM9EJ-S takes the arisen excep-
tions according to the following priority order:
• N: Negative, Z: Zero, C: Carry, and V: Overflow are the four ALU flags
• The Sticky Overflow (Q) flag can be set by certain multiply and fractional arithmetic
• The J bit in the CPSR indicates when the ARM9EJ-S core is in Jazelle state, where:
• Mode: five bits to encode the current processor mode
• Fast interrupt (FIQ)
• Normal interrupt (IRQ)
• Data and Prefetched aborts (Abort)
• Undefined instruction (Undefined)
• Software interrupt and Reset (Supervisor)
• Reset (highest priority)
• Data Abort
• FIQ
• IRQ
• Prefetch Abort
• BKPT, Undefined instruction, and Software Interrupt (SWI) (Lowest priority)
instructions like QADD, QDADD, QSUB, QDSUB, SMLAxy, and SMLAWy needed to achieve
DSP operations.
The Q flag is sticky in that, when set by an instruction, it remains set until explicitly cleared by
an MSR instruction writing to the CPSR. Instructions cannot execute conditionally on the
status of the Q flag.
ARM9EJ-S supports five types of exceptions. Each type drives the ARM9EJ-S in a privi-
– J = 0: The processor is in ARM or Thumb state, depending on the T bit
– J = 1: The processor is in Jazelle state.
shows the status register format, where:
N Z C V Q
31 30 29 28 27
24
J
Jazelle state bit
Reserved
Sticky Overflow
Overflow
Carry/Borrow/Extend
Zero
Negative/Less than
Reserved
I F T
7 6 5
Mode
0
Mode bits
Thumb state bit
FIQ disable
IRQ disable
6289D–ATARM–3-Oct-11