SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 716

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

40.6.3
716
31
31
31
31
31
31
To Receive Word transfers
To Receive Halfword Transfers
To Receive 10-bit Samples
AT91SAM9R64/RL64
Variable Sample Rate
Byte0[7:0]
–
–
–
–
–
Data received on appropriate slot: data[19:0] = {Byte2[3:0], Byte1[7:0], Byte0[7:0]}.
Word stored in AC’97 Controller Channel x Receive Holding Register (AC97C_CxRHR)
(Received Data)
Data is read from AC’97 Controller Channel x Receive Holding Register (AC97C_CxRHR) when
Channel x data size is greater than 16 bits and when big-endian mode is enabled (data written to
memory).
Data received on appropriate slot: data[19:0] = {0x0, Byte1[7:0], Byte0[7:0]}.
Halfword stored in AC’97 Controller Channel x Receive Holding Register (AC97C_CxRHR)
(Received Data).
Data is read from AC’97 Controller Channel x Receive Holding Register (AC97C_CxRHR) when
data size is equal to 16 bits and when big-endian mode is enabled.
Data received on appropriate slot: data[19:0] = {0x000, Byte1[1:0], Byte0[7:0]}.Halfword stored
in AC’97 Controller Channel x Receive Holding Register (AC97C_CxRHR) (Received Data)
Data read from AC’97 Controller Channel x Receive Holding Register (AC97C_CxRHR) when
data size is equal to 10 bits and when big-endian mode is enabled.
The problem of variable sample rate can be summarized by a simple example. When passing a
44.1 kHz stream across the AC-link, for every 480 audio output frames that are sent across, 441
of them must contain valid sample data. The new AC’97 standard approach calls for the addition
of “on-demand” slot request flags. The AC‘97 Codec examines its sample rate control register,
the state of its FIFOs, and the incoming SDATA_OUT tag bits (slot 0) of each output frame and
then determines which SLOTREQ bits to set active (low). These bits are passed from the AC97
24
24
24
24
24
24
23
23
23
23
23
23
–
Byte1[7:0]
20
.
–
–
–
–
19
Byte2[3:0]
16
16
16
16
16
16
15
15
15
15
15
{0x0, Byte2[3:0]}
Byte0[7:0]
Byte1[7:0]
Byte1[7:0]
Byte0[7:0]
–
15
10
Byte1
9
[1:0]
8
8
8
8
8
8
7
7
7
7
7
7
0x00
Byte0[7:0]
Byte0[7:0]
Byte1[7:0]
Byte0[7:0]
6289D–ATARM–3-Oct-11
0x00
3
Byte1
1
[1:0]
0
0
0
0
0
0