SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 741

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

41.4.7
41.4.8
41.4.8.1
6289D–ATARM–3-Oct-11
Transfer Without DMA
Handling Transactions with USB V2.0 Device Peripheral
Setup Transaction
Important. If the DMA is not to be used, it is necessary that it be disabled because otherwise it
can be enabled by previous versions of software without warning. If this should occur, the DMA
can process data before an interrupt without knowledge of the user.
The recommended means to disable DMA is as follows:
The setup packet is valid in the DPR while RX_SETUP is set. Once RX_SETUP is cleared by
the application, the UDPHS accepts the next packets sent over the device endpoint.
When a valid setup packet is accepted by the UDPHS:
An endpoint interrupt is generated while RX_SETUP in the UDPHS_EPTSTAx register is not
cleared. This interrupt is carried out to the microcontroller if interrupts are enabled for this
endpoint.
• the UDPHS device automatically acknowledges the setup packet (sends an ACK response)
• payload data is written in the endpoint
• sets the RX_SETUP interrupt
• the BYTE_COUNT field in the UDPHS_EPTSTAx register is updated
// Reset IP UDPHS
// With OR without DMA !!!
AT91C_UDPHS_DMA_CHANNEL_NBR)>>4); i++ ) {
// RESET endpoint canal DMA:
command
// Disable endpoint
// Reset endpoint config
// Reset DMA channel (Buff count and Control field)
STOP command
// Reset DMA channel 0 (STOP)
command
// Clear DMA channel status (read the register for clear it)
AT91C_BASE_UDPHS->UDPHS_DMA[i].UDPHS_DMASTATUS;
}
AT91C_BASE_UDPHS->UDPHS_CTRL &= ~AT91C_UDPHS_EN_UDPHS;
AT91C_BASE_UDPHS->UDPHS_CTRL |= AT91C_UDPHS_EN_UDPHS;
for( i=1; i<=((AT91C_BASE_UDPHS->UDPHS_IPFEATURES &
// DMA stop channel command
AT91C_BASE_UDPHS->UDPHS_DMA[i].UDPHS_DMACONTROL = 0;
AT91C_BASE_UDPHS->UDPHS_EPT[i].UDPHS_EPTCTLDIS |= 0XFFFFFFFF;
AT91C_BASE_UDPHS->UDPHS_EPT[i].UDPHS_EPTCTLCFG = 0;
AT91C_BASE_UDPHS->UDPHS_DMA[i].UDPHS_DMACONTROL = 0x02;
AT91C_BASE_UDPHS->UDPHS_DMA[i].UDPHS_DMACONTROL = 0;
AT91C_BASE_UDPHS->UDPHS_DMA[i].UDPHS_DMASTATUS =
AT91SAM9R64/RL64
// STOP
// STOP
// NON
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