SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 582

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

6289D–ATARM–3-Oct-11
3. After the DMAC selected channel has been programmed, enable the channel by writing
4. When the buffer transfer has completed, the DMAC reloads the DMAC_SADDRx,
5. The DMAC transfer proceeds as follows:
a. Write the starting source address in the DMAC_SADDRx register for channel x.
b. Write the starting destination address in the DMAC_DADDRx register for channel
c. Program DMAC_CTRLAx, DMAC_CTRLBx and DMAC_CFGx according to Row
d. Write the control information for the DMAC transfer in the DMAC_CTRLAx and
e. If source picture-in-picture mode is enabled (DMAC_CTRLBx.SPIP is enabled),
f.
g. Write the channel configuration information into the DMAC_CFGx register for chan-
a ‘1’ to the DMAC_CHER.ENABLE[n] bit where is the channel number. Make sure that
bit 0 of the DMAC_EN register is enabled.
DMAC_DADDRx and DMAC_CTRLAx registers. Hardware sets the buffer Complete
interrupt. The DMAC then samples the row number as shown in
575. If the DMAC is in Row 1, then the DMAC transfer has completed. Hardware sets
the transfer complete interrupt and disables the channel. So you can either respond to
the Buffer Complete or Chained buffer transfer Complete interrupts, or poll for the
Channel Enable in the Channel Status Register (DMAC_CHSR.ENABLE[n]) until it is
disabled, to detect when the transfer is complete. If the DMAC is not in Row 1, the next
step is performed.
a. If interrupts is un-masked (DMAC_EBCIMR.BTC[x] = ‘1’, where x is the channel
b. If the buffer complete interrupt is masked (DMAC_EBCIMR.BTC[x] = ‘1’, where x is
– Set up the transfer characteristics, such as:
– Transfer width for the source in the SRC_WIDTH field.
– Transfer width for the destination in the DST_WIDTH field.
– Source AHB master interface layer in the SIF field where source resides.
– Destination AHB master interface layer in the DIF field where destination resides.
– Incrementing/decrementing or fixed address for source in SRC_INCR field.
– Incrementing/decrementing or fixed address for destination in DST_INCR field.
x.
10 as shown in
‘0’.
DMAC_CTRLBx register for channel x. For example, in the register, you can pro-
gram the following:
program the DMAC_SPIPx register for channel x.
If destination picture-in-picture is enabled (DMAC_CTRLBx.DPIP), program the
DMAC_DPIPx register for channel x.
nel x. Ensure that the reload bits, DMAC_CFGx.SRC_REP,
DMAC_CFGx.DST_REP and DMAC_CTRLBx.AUTO are enabled.
number) hardware sets the buffer complete interrupt when the buffer transfer has
completed. It then stalls until the STALLED[n] bit of DMAC_CHSR register is
cleared by software, writing ‘1’ to DMAC_CHER.KEEPON[n] bit where n is the
channel number. If the next buffer is to be the last buffer in the DMAC transfer, then
the buffer complete ISR (interrupt service routine) should clear the automatic mode
bit in the DMAC_CTRLBx.AUTO bit. This put the DMAC into Row 1 as shown in
Table 37-1 on page
fer, then the reload bits should remain enabled to keep the DMAC in Row 4.
the channel number), then hardware does not stall until it detects a write to the buf-
fer complete interrupt enable register DMAC_EBCIER register but starts the next
buffer transfer immediately. In this case software must clear the automatic mode bit
Table 37-1 on page
575. If the next buffer is not the last buffer in the DMAC trans-
575. Program the DMAC_DSCRx register with
AT91SAM9R64/RL64
Table 37-1 on page
582