SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 884

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

47.2.4.2
47.2.4.3
47.2.4.4
47.2.4.5
47.2.5
47.2.5.1
884
AT91SAM9R64/RL64
Reset Controller (RSTC)
MCI: SDIO Interrupt does not work with slots other than A when 1-bit databus is selected
MCI: Data Timeout Error Flag
MCI: Data Write Operation and number of bytes
MCI: Flag Reset is not correct in half duplex mode
RSTC: Reset during SDRAM Accesses
conflict can occur on data line0 if the MCI sends data to the card while the card is still busy.The
behavior is correct for CMD12 command (STOP_TRANSFER).
None
If 1-bit data bus width and on slots other than slot A, the SDIO interrupt can not be captured. The
sample is made on the wrong data line.
None
As the data Timeout error flag checking the Naac timing cannot rise, the MCI can be stalled wait-
ing indefinitely the Data start bit.
A STOP command must be sent with a software timeout.
The Data Write operation with a number of bytes less than 12 is impossible.
The PDC counters must always be equal to 12 bytes for data transfers lower than 12 bytes. The
BLKLEN or BCNT field are used to specify the real count number.
In half duplex mode, the reset of the flags ENDRX, RXBUFF, ENDTX and TXBUFE can be
incorrect. These flags are reset correctly after a PDC channel enable.
Enable the interrupts related to ENDRX, ENDTX, RXBUFF and TXBUFE only after enabling the
PDC channel by writing PDC_TXTEN or PDC_RXTEN.
When a User Reset occurs during SDRAM read access, the SDRAM clock is turned off while
data are ready to be read on the data bus. The SDRAM maintains the data until the clock
restarts.
If the User Reset is programmed to assert a general reset, the data maintained by the SDRAM
leads to a data bus conflict and adversely affects the boot memories connected on the EBI:
In the interrupt routine, power down the SDRAM properly and perform Peripheral and Processor
Reset with software in assembler.
• NAND Flash boot functionality, if the system boots out of internal ROM.
• NOR Flash boot, if the system boots on an external memory connected on the EBI CS0.
1. Avoid User Reset to generate a system reset.
2. Trap the User Reset with an interrupt.
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
6289D–ATARM–3-Oct-11