SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 833

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Figure 43-5. EOCx and DRDY Flag Behavior
Figure 43-6. GOVRE and OVREx Flag Behavior
6289D–ATARM–3-Oct-11
(ADC_CHSR)
(ADC_CHSR)
ADC_LCDR
ADC_CDR0
ADC_CDR1
(ADC_SR)
(ADC_SR)
(ADC_SR)
(ADC_SR)
(ADC_SR)
GOVRE
ADTRG
DRDY
OVRE0
EOC0
EOC1
CH0
CH1
(ADC_CHSR)
(ADC_SR)
(ADC_SR)
EOCx
DRDY
If the
converted, the corresponding Overrun Error (OVRE) flag is set in the
Register”.
In the same way, new data converted when DRDY is high sets the bit GOVRE (General Overrun
Error) in the
The OVRE and GOVRE flags are automatically cleared when the
read.
CHx
Undefined Data
Undefined Data
“TSADCC Channel Data Register x (x = 0..5)”
Write the ADC_CR
with START = 1
SHTIM
SHTIM
Undefined Data
“TSADCC Status
Conversion
Conversion
Time
SHTIM
Read the ADC_CDRx
Data A
Conversion
Register”.
Data A
Data B
SHTIM
Write the ADC_CR
with START = 1
SHTIM
Conversion
is not read before further incoming data is
Conversion
Data B
Time
AT91SAM9R64/RL64
Read the ADC_LCDR
Data C
Read ADC_CDR1
Data C
“TSADCC Status
Read ADC_SR
Read ADC_CDR0
“TSADCC Status
Register”is
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