SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 887

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

47.2.7
47.2.7.1
47.2.8
47.2.8.1
47.2.9
47.2.9.1
6289D–ATARM–3-Oct-11
Serial Peripheral Interface (SPI)
Shutdown Controller
Static Memory Controller (SMC)
SPI: Bad Serial Clock Generation on second chip_select when SCBR = 1, CPOL = 1 and NCPHA = 0
SHDN Signal may be Driven to Low Level Voltage During Device Power-on
SMC: Chip Select Parameters Modification
then the first clock cycle time generated by the RK pin is equal to MCK/(2 x (DIV +1)) instead of
MCK/(2 x DIV).
None.
If the SPI is used in the following configuration:
then an additional pulse will be generated on output PSCK during the second transfer.
Do not use a multiple Chip Select configuration where at least one SCRx register is configured
with SCBR = 1 and the others differ from 1 if CPHA = 0 and CPOL = 1.
If all chip selects are configured with Baudrate = 1, the issue does not appear.
If only VDDBU is powered during boot sequence (No VDDCORE), the SHDN signal may be
driven to low level voltage after a delay. This delay is linked to the startup time of the slow clock
selected by OSCSEL signal.
If SHDN pin is connected to the Enable pin (EN) of the VDDCORE regulator, VDDCORE estab-
lishment does not occur and the system does not start.
1. VDDCORE must be established within the delay corresponding to the startup time of the slow
clock selected by OSCSEL.
2. Add a glue logic to latch the rising edge of the SHDN signal. The reset of the latch output
(EN_REG) can be connected to a PIO and used to enter the shutdown mode.
The user must not change the configuration parameters of an SMC Chip Select (Setup, Pulse,
Cycle, Mode) if accesses are performed on this CS during the modification.
For example, the modification of the Chip Select 0 (CS0) parameters, while fetching the code
from a memory connected on this CS0, may lead to unpredictable behavior.
The code used to modify the parameters of an SMC Chip Select can be executed from the inter-
nal RAM or from a memory connected to another Chip Select.
• master mode
• CPOL=1 and NCPHA =0
• multiple chip selects used with one transfer with Baud rate (SCBR) equal to 1 (i.e., when
• transmit with the slowest chip select and then with the fastest one
serial clock frequency equals the system clock frequency) and the other transfers set with
SCBR not equal to 1
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
AT91SAM9R64/RL64
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