SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 82

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

14.7.3.2
14.8
6289D–ATARM–3-Oct-11
Hardware and Software Constraints
Communication Endpoints
The device also handles some class requests defined in the CDC class.
Table 14-4.
Unhandled requests are STALLed.
There are two communication endpoints and endpoint 0 is used for the enumeration process.
Endpoint 1 is a 512-byte Bulk OUT endpoint and endpoint 2 is a 512-byte Bulk IN endpoint.
SAM-BA Boot commands are sent by the host through the endpoint 1. If required, the message
is split by the host into several data payloads by the host driver.
If the command requires a response, the host can send IN transactions to pick up the response.
The MCI, the SPI and NAND Flash drivers use several PIOs in alternate functions to communi-
cate with devices. Care must be taken when these PIOs are used by the application. The
devices connected could be unintentionally driven at boot time, and electrical conflicts between
peripherals output pins and the connected devices may appear.
To assure correct functionality, it is recommended to plug in critical devices to other pins.
Table 14-5
are driven during the boot sequence for a period of less than 1 second if no correct boot program
is found.
For the DataFlash driven by the SPCK signal at 8 MHz, the time to download 60 K bytes is
reduced to 200 ms.
Request
SET_LINE_CODING
GET_LINE_CODING
SET_CONTROL_LINE_STATE
• A 12 MHz Crystal is mandatory in order to generate correctly 480 MHz clock necessary for
• No Bypass Mode.
• The SD Card, NAND Flash and DataFlash downloaded code size must be inferior to 56 K
• The code is always downloaded from the DataFlash or NAND Flash device address
• The downloaded code must be position-independent or linked at address 0x0000_0000.
• The DataFlash must be connected to NPCS0 of the SPI.
the USB High Speed Device and to generate the 48 MHz System clock.
bytes.
0x0000_0000 to the address 0x0000_0000 of the internal SRAM (after remap).
contains a list of pins that are driven during the boot program execution. These pins
Handled Class Requests
Definition
Configures DTE rate, stop bits, parity and number of
character bits.
Requests current DTE rate, stop bits, parity and number
of character bits.
RS-232 signal used to tell the DCE device the DTE
device is now present.
AT91SAM9R64/RL64
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