SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 711
SAM9RL64
Manufacturer Part Number
SAM9RL64
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9260.pdf
(290 pages)
3.SAM9261.pdf
(248 pages)
4.SAM9R64.pdf
(903 pages)
5.SAM9R64.pdf
(52 pages)
Specifications of SAM9RL64
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
118
Ext Interrupts
118
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
5
Ssc
2
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
6
Adc Resolution (bits)
10
Adc Speed (ksps)
220
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- SAM9260 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9R64 PDF datasheet #4
- SAM9R64 PDF datasheet #5
- Current page: 711 of 903
- Download datasheet (13Mb)
40.6.2
Figure 40-4. Logical Channel Assignment
6289D–ATARM–3-Oct-11
(Controller Output)
(Codec output)
AC‘97 Controller Channel Organization
AC97RX
AC97FS
AC97TX
Slot #
AC97C_ICA = 0x0000_0009
AC97C_OCA = 0x0000_0209
TAG
TAG
0
The AC’97 Controller features a Codec channel and 2 logical channels; Channel A and Channel
B.
The Codec channel controls AC‘97 Codec registers, it enables write and read configuration val-
ues in order to bring the AC97 Codec to an operating state. The Codec channel always runs slot
1 and slot 2 exclusively, in both input and output directions.
Channel A and Channel B transfer data to/from AC97 codec. All audio samples and modem
data must transit by these two channels. However, Channel A is connected to PDC channels
thus making it suitable for audio streaming applications.
Each slot of the input or the output frame that belongs to this range [3 to 12] can be operated by
either Channel A or Channel B. The slot to channel assignment is configured by two registers:
The AC’97 Controller Input Channel Assignment Register (AC97C_ICA) configures the input slot
to channel assignment. The AC’97 Controller Output Channel Assignment Register
(AC97C_OCA) configures the output slot to channel assignment.
A slot can be left unassigned to a channel by the AC’97 Controller. Slots 0, 1,and 2 cannot be
assigned to Channel A or to Channel B through the AC97C_OCA and AC97C_ICA Registers.
The width of sample data, that transit via Channel A and Channel B varies and can take one of
these values; 10, 16, 18 or 20 bits.
STATUS
• AC’97 Controller Input Channel Assignment Register (AC97C_ICA)
• AC’97 Controller Output Channel Assignment Register (AC97C_OCA)
ADDR
ADDR
CMD
Codec Channel
1
Codec Channel
STATUS
DATA
DATA
CMD
2
3
L Front
LEFT
PCM
PCM
Channel A
Channel A
R Front
RIGHT
4
PCM
PCM
LINE 1
LINE 1
5
DAC
DAC
6
Center
PCM
PCM
MIC
L SURR
RSVED
7
PCM
R SURR
RSVED
PCM
8
AT91SAM9R64/RL64
RSVED
PCM
9
LFE
LINE 2
LINE 2
10
ADC
DAC
11
HSET
HSET
ADC
DAC
STATUS
12
CTRL
IO
IO
711
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