SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 801
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SAM9RL64
Manufacturer Part Number
SAM9RL64
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9260.pdf
(290 pages)
3.SAM9261.pdf
(248 pages)
4.SAM9R64.pdf
(903 pages)
5.SAM9R64.pdf
(52 pages)
Specifications of SAM9RL64
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
118
Ext Interrupts
118
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
5
Ssc
2
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
6
Adc Resolution (bits)
10
Adc Speed (ksps)
220
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- SAM9260 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9R64 PDF datasheet #4
- SAM9R64 PDF datasheet #5
- Current page: 801 of 903
- Download datasheet (13Mb)
41.5.26
Name:
Access Type:
• CHANN_ENB (Channel Enable Command)
0 = DMA channel is disabled at and no transfer will occur upon request. This bit is also cleared by hardware when the chan-
nel source bus is disabled at end of buffer.
If the UDPHS_DMACONTROL register LDNXT_DSC bit has been cleared by descriptor loading, the firmware will have to
set the corresponding CHANN_ENB bit to start the described transfer, if needed.
If the UDPHS_DMACONTROL register LDNXT_DSC bit is cleared, the channel is frozen and the channel registers may
then be read and/or written reliably as soon as both UDPHS_DMASTATUS register CHANN_ENB and CHANN_ACT flags
read as 0.
If a channel request is currently serviced when this bit is cleared, the DMA FIFO buffer is drained until it is empty, then the
UDPHS_DMASTATUS register CHANN_ENB bit is cleared.
If the LDNXT_DSC bit is set at or after this bit clearing, then the currently loaded descriptor is skipped (no data transfer
occurs) and the next descriptor is immediately loaded.
1 = UDPHS_DMASTATUS register CHANN_ENB bit will be set, thus enabling DMA channel data transfer. Then any pend-
ing request will start the transfer. This may be used to start or resume any requested transfer.
• LDNXT_DSC: Load Next Channel Transfer Descriptor Enable (Command)
0 = no channel register is loaded after the end of the channel transfer.
1 = the channel controller loads the next descriptor after the end of the current transfer, i.e. when the
UDPHS_DMASTATUS/CHANN_ENB bit is reset.
If the UDPHS_DMA CONTROL/CHANN_ENB bit is cleared, the next descriptor is immediately loaded upon transfer
request.
6289D–ATARM–3-Oct-11
BURST_LCK
LDNXT_DSC
31
23
15
–
7
0
0
1
1
UDPHS DMA Channel Control Register
DESC_LD_IT
30
22
14
Read/Write
–
6
CHANN_ENB
UDPHS_DMACONTROLx [x = 1..5]
0
1
0
1
END_BUFFIT
29
21
13
–
5
Stop now
Run and stop at end of buffer
Load next descriptor now
Run and link at end of buffer
END_TR_IT
28
20
12
–
4
BUFF_LENGTH
BUFF_LENGTH
Description
END_B_EN
27
19
11
–
3
END_TR_EN
AT91SAM9R64/RL64
26
18
10
–
2
LDNXT_DSC
25
17
9
–
1
CHANN_ENB
24
16
8
–
0
801
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