Z16FMC64AG20SG Zilog, Z16FMC64AG20SG Datasheet - Page 92

• Manufacturer Part Number: Z16FMC64AG20SG
• Description: Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC64AG20SG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: 0 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / Rohs Status: Details

PS028702-1210
PWM SINGLE and DUAL OUTPUT Modes
In PWM SINGLE OUTPUT mode, the timer outputs a PWM output signal through a
GPIO Port pin. In PWM DUAL OUTPUT mode, the timer outputs a PWM output signal
and also its complement through two GPIO port pins. The timer first counts up to the 
16-bit PWM match value stored in the timer PWM high and low byte registers. When the
timer count value matches the PWM value, the timer output toggles. The timer continues
counting until it reaches the Reload value stored in the timer reload high and low byte reg-
isters. When it reaches the Reload value, the timer generates an interrupt. The count value
in the timer high and low byte registers is reset to
The timer output signal begins with value =
timer value matches the PWM value. The timer output signal returns to
timer reaches the Reload value and is reset to
In PWM DUAL OUTPUT mode, the timer also generates a second PWM output signal,
timer output complement (TOUT). A programmable deadband is configured (
to delay (0 to 128 system clock cycles) the Low to a High (inactive to active) output tran-
sitions on these two pins. This configuration ensures a time gap between the deassertion of
one PWM output to the assertion of its complement.
Observe the following steps to configure a timer for PWM SINGLE or DUAL OUTPUT
mode and initiate the PWM operation:
1. Write to the timer control registers to:
2. Write to the timer high and low byte registers to set the starting count value (typically
3. Write to the PWM high and low byte registers to set the PWM value.
4. Write to the timer reload high and low byte registers to set the Reload value (PWM
5. Enable the timer interrupt, if required and set the timer interrupt priority by writing to
6. Configure the associated GPIO port pin(s) for the timer output alternate function.
7. Write to the Timer Control 1 Register to enable the timer and initiate counting.
–
–
–
–
–
0001H
first timer reset in PWM mode, counting always begins at the reset value of
period). The Reload value must be greater than the PWM value.
the relevant interrupt registers.
Disable the timer.
Configure the timer for the selected PWM mode.
Set the prescale value.
Set the initial logic level (High or Low) and PWM High or Low transition for the
timer output alternate function with the TPOL bit.
Set the deadband delay (DUAL OUTPUT mode) with the
). The starting count value only affects the first pass in PWM mode. After the
P R E L I M I N A R Y
TPOL
0001H
Z16FMC Series Motor Control MCUs
0001H
and then transits to
.
and counting resumes.
Product Specification
PWMD
TPOL
TPOL
field.
, when the
PWMD
after the
0001H
Timers
field)
.
70