Z16FMC64AG20SG Zilog, Z16FMC64AG20SG Datasheet - Page 252

• Manufacturer Part Number: Z16FMC64AG20SG
• Description: Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC64AG20SG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: 0 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / Rohs Status: Details

Table 121. DMA Priority
PS028702-1210
DMA Priority
5. Fetch the TXLN length from the descriptor and place it in the DMAxTXLN register in
6. After the reads have been completed, the DMA starts looking for requests and transfer
7. When the DMA receives the Request EOF signal, it performs the following operations
8. If the
9. After a new DMAxLAR address has been updated, the DMA goes back to step 2
The DMA priority is based upon the final channel serviced. After a channel is serviced it
becomes the lowest-priority channel. Table 121 lists the DMA priority.
Last Channel Serviced
DMA0
DMA1
DMA2
DMA3
the DMA channel.
data until the transfer length reaches zero or the DMA receives a Request EOF signal.
based upon the
–
–
–
descriptor.
above and fetches the control/status byte.
00: The DMA writes the descriptor Control/Status word with the
to 0.
01: The DMA requests status from the peripheral. It then writes the descriptor
Control/Status word with the
the peripheral. The DMA then writes the TXLN length to the descriptor.
1X: The DMA does not modify the descriptor.
HALT
bit is set the DMA closes the current buffer but does not fetch the next
LOOP
and
P R E L I M I N A R Y
DMA Priority
DMA1 (Highest)
DMA2
DMA3
DMA0 (Lowest)
DMA2 (Highest)
DMA3
DMA0
DMA1 (Lowest)
DMA3 (Highest)
DMA0
DMA1
DMA2 (Lowest)
DMA 0 (Highest)
DMA 1
DMA 2
DMA 3 (Lowest)
EOF
bit:
DMAxEN
Z16FMC Series Motor Control MCUs
bit reset to 0 and the status returned from
Product Specification
DMAxEN
DMA Controller
bit reset
230