Z16FMC64AG20SG Zilog, Z16FMC64AG20SG Datasheet - Page 172

• Manufacturer Part Number: Z16FMC64AG20SG
• Description: Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC64AG20SG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: 0 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / Rohs Status: Details

PS028702-1210
Throughput
ESPI Clock Phase and Polarity Control
enable (DIRQE) bit is set. The TDRE and RDRF signals also generate transmit and
receive DMA requests.
such a case, either the TDRE or RDRF interrupts/DMA requests is disabled to minimize
software/DMA overhead. Unidirectional data transfer is supported by setting the
ESPIEN1, 0 bits in the control register to
move the data, the transmit and receive data interrupts are disabled through the DIRQE bit
of the control register. In this case error interrupts still occurs and must be handled directly
by the software.
In MASTER mode, the maximum SCK rate supported is one-half the system clock fre-
quency. This rate is achieved by programming the value
low register pair. Though each character is transferred at this rate, it is unlikely that soft-
ware interrupt routines or DMA keeps up with this rate. In SPI mode the transfer will auto-
matically pause between characters until the current receive character is read and the next
transmit data value is written.
In SLAVE mode, the transfer rate is controlled by the master. As long as the TDRE and
RDRF interrupt or DMA requests are serviced before the next character transfer completes
the slave will keep up with the master. In SLAVE mode, the baud rate is restricted to a
maximum of one-fourth of the system clock frequency to allow for synchronization of the
SCK input to the internal system clock.
The ESPI supports four combinations of SCK phase and polarity using two bits in the
ESPI control register. The clock polarity bit, CLKPOL, selects an active High or active
Low clock and has no effect on the transfer format. The clock phase bit, PHASE, selects
one of two fundamentally different transfer formats. The data is output a half-cycle before
the receive clock edge which provides a half cycle of setup and hold time. Table 85 lists
the ESPI clock phase and polarity operation parameters.
Table 85. ESPI Clock Phase (PHASE) and Clock Polarity (CLKPOL) Operation
PHASE
0
0
1
1
In many cases the software application is only moving information in one direction. In
CLKPOL
0
1
0
1
P R E L I M I N A R Y
SCK Transmit
Falling
Falling
Rising
Rising
Edge
10
or
Z16FMC Series Motor Control MCUs
SCK Receive Edge
01
. If the DMA engine is being used to
Enhanced Serial Peripheral Interface
Falling
Falling
Rising
Rising
0001H
into the baud rate high/
Product Specification
SCK Idle
State
High
High
Low
Low
150