Z16FMC64AG20SG Zilog, Z16FMC64AG20SG Datasheet - Page 193

Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D

Z16FMC64AG20SG

Manufacturer Part Number
Z16FMC64AG20SG
Description
Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
Manufacturer
Zilog
Series
Z16FMCr
Datasheet

Specifications of Z16FMC64AG20SG

Processor Series
Z16FMC
Core
ZNEO
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
64 KB
Data Ram Size
4 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
46
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
LQFP-64
Development Tools By Supplier
Z16FMC28200KITG
Minimum Operating Temperature
0 C
Core Processor
ZNEO
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
46
Eeprom Size
-
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
Z16FMC64AG20SG
Manufacturer:
Zilog
Quantity:
161
Part Number:
Z16FMC64AG20SG
Manufacturer:
Zilog
Quantity:
10 000
I
Architecture
PS028702-1210
2
C Master/Slave Controller
The I
col. The I
bidirectional lines. Features of the I
Figure 33 displays the architecture of the I
Operates in MASTER/SLAVE or SLAVE ONLY modes
Supports arbitration in a Multi-Master environment (MASTER/SLAVE mode)
Supports data rates up to 400 kbps
7-bit or 10-bit slave address recognition (interrupt only on address match)
Optional general call address recognition
Optional digital filter on receive SDA and SCL lines
Optional interactive receive mode allows software interpretation of each received
address and/or data byte before acknowledging
Unrestricted number of data bytes per transfer
Baud Rate Generator (BRG) is used as a general purpose timer with interrupt if the I
controller is disabled
2
C Master/Slave Controller makes the Z16FMC bus compatible with the I
2
C bus consists of the serial data signal (SDA) and a serial clock (SCL) signal
P R E L I M I N A R Y
2
C Controller include:
2
C Controller.
Z16FMC Series Motor Control MCUs
I2C Master/Slave Controller
Product Specification
2
C proto-
2
C 
171

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