Z16FMC64AG20SG Zilog, Z16FMC64AG20SG Datasheet - Page 328

• Manufacturer Part Number: Z16FMC64AG20SG
• Description: Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC64AG20SG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: 0 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / Rohs Status: Details

(Output)
(Output)
SDA
nput)
PS028702-1210
SDA
SCL
I
UART Timing
2
C Timing
T2
Figure 67 and Table 182 provide timing information for I
Table 182. I
Figure 68 and Table 183 provide timing information for UART pins for the case where the
Clear To Send input pin (CTS) is used for flow control. In this example, it is assumed that
the Driver Enable polarity has been configured to be Active Low and is represented here
by DE. The CTS to DE assertion delay (T1) assumes the UART Transmit Data Register
has been loaded with data prior to CTS assertion.
Parameter
I
2
C
T
T
T
1
2
3
Input Data
2
C Timing
Abbreviation
SCL Fall to SDA output delay
SDA Input to SCL rising edge Setup Time 0
SDA Input to SCL falling edge Hold Time
Figure 67. I
P R E L I M I N A R Y
T3
2
T1
C Timing
Z16FMC Series Motor Control MCUs
Output Data
2
C pins.
SCL period/4
0
Product Specification
Electrical Characteristics
Min
Delay (ns)
Max
306